AD9884A/PCB AD [Analog Devices], AD9884A/PCB Datasheet - Page 9

• Manufacturer Part Number: AD9884A/PCB
• Description: 100 MSPS/140 MSPS Analog Flat Panel Interface
• Manufacturer: AD [Analog Devices]

CONTROL REGISTER MAP
The AD9884A is initialized and controlled by a set of registers
that determine the operating modes. An external controller is
employed to write and read the control registers through the
2-line serial interface port.
Reg Bit Default
PLL Divider Control
00
01
01
Input Gain
02
03
04
Input Offset
05
05
06
06
07
07
Clamp Timing
08
09
General Control 1
0A 7
0A 6
0A 5
0A 4
0A 3
0A 2
0A 1
0A 0
Clock Generator Control
0B
0B
0C 7
0C 6–5
0C 4–2
0C 1–0
General Control 2
0D 7–5 000
0D 4
0D 3–1
0D 0
0E
REV. B
7–0 01101001 PLLDIVM
7–4 1101
3–0
7–0 10000000 REDGAIN
7–0 10000000 GRNGAIN Green Channel Gain Adjust
7–0 10000000 BLUGAIN
7–2 100000
1–0
7–2 100000
1–0
7–2 100000
1–0
7–0 10000000 CLPLACE
7–0 10000000 CLDUR
7–3 10000
2–0
7–0 00000000
••••
••••••
••••••
••••••
1
•
••
•••
••••
•••••
••••••
•••••••
•••••
0
•
•••
••••••
•••
••••
•••••••
•••••••
1
•••••••
01
1
••••••
•••••
1
•••••
001
0
•••••
••••
0000
••••
0
••••
000
Table II. Control Register Map
•••
1
•••
000
00
00
00
••
0
00
••
••
••
••
•
0
•
0
Mnemonic
PLLDIVL
REDOFST
GRNOFST Green Channel Offset Adjust
BLUOFST
DEMUX
PAR
HSPOL
CSTPOL
EXTCLMP Clamp Signal Source
CLAMPOL Clamp Signal Polarity
EXTCLK
PHASE
VCORNGE VCO Range Select
CURRENT Charge Pump Current
OUTPHASE Output Port Phase
REVID
Function
PLL Divide Ratio MSBs
PLL Divide Ratio LSBs
Reserved, Set to Zero
Red Channel Gain Adjust
Blue Channel Gain Adjust
Red Channel Offset Adjust
Reserved, Set to Zero
Reserved, Set to Zero
Blue Channel Offset Adjust
Reserved, Set to Zero
Clamp Placement
Clamp Duration
Output Port Select
Output Timing Select
HSYNC Polarity
COAST Polarity
External Clock Select
Reserved, Set to Zero
Clock Phase Adjust
Reserved, Set to Zero
Reserved, Set to Zero
Reserved, Set to Zero
Reserved, Set to Zero
Die Revision ID
Reserved, Set to Zero
Reserved, Set to Zero
–9–
Reg
00
01
02
03
04
05
06
07
CONTROL REGISTER DETAIL
PLL DIVIDER CONTROL
The eight most significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The PLL derives a master clock from an incoming HSYNC
signal. The master clock frequency is then divided by an integer
value, and the divider’s output is phase-locked to HSYNC. This
PLLDIV value determines the number of pixel times (pixels
plus horizontal blanking overhead) per line. This is typically
20% to 30% more than the number of active pixels in the display.
The 12-bit value of PLLDIV supports divide ratios from 2 to
4095. The higher the value loaded in this register, the higher
the resulting clock frequency with respect to a fixed HSYNC
frequency.
VESA has established some standard timing specifications,
which will assist in determining the value for PLLDIV as a
function of horizontal and vertical display resolution and frame
rate (Table VII). However, many computer systems do not
conform precisely to the recommendations, and these numbers
should be used only as a guide. The display system manufac-
turer should provide automatic or manual means for optimizing
PLLDIV. An incorrectly set PLLDIV will usually produce one
or more vertical noise bars on the display. The greater the error,
the greater the number of bars produced.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69h, PLLDIVL = Dxh).
The four least significant bits of the 12-bit PLL divide ratio
PLLDIV. The operational divide ratio is PLLDIV + 1.
The power-up default value of PLLDIV is 1693 (PLLDIVM =
69h, PLLDIVL = Dxh).
00
01
Value
01101001
1101 0000
10000000
10000000
10000000
100000 00
100000 00
100000 00
7–0
7–4
Table III. Default Register Values
PLLDIVM
PLLDIVL
69h
D0h
80h
80h
80h
80h
80h
80h
PLL Divide Ratio MSBs
Reg
08
09
0A
0B
0C
0D
0E
0F
PLL Divide Ratio LSBs
Value
10000000
11110100
10000 000
0 01 001 00
10000000
00000000
0000xxx0
00000000
AD9884A
80h
F4h
80h
24h
80h
00h
0xh
00h