ADV7129KS AD [Analog Devices], ADV7129KS Datasheet - Page 3

• Manufacturer Part Number: ADV7129KS
• Description: 192-Bit, 360 MHz True-Color Video DAC with Onboard PLL
• Manufacturer: AD [Analog Devices]

TIMING SPECIFICATIONS
Parameter
CLOCK CONTROL & PIXEL PORT
MPU PORT
ANALOG OUTPUTS
PLL PERFORMANCE
NOTES
1
2
3
4
5
6
Specifications subject to change without notice.
REV. 0
TTL inputs values are 0 V to 3 V with input rise/fall times 3 ns, measured between the 10% and 90% points. Timing reference points at 50% for inputs and out-
Temperature range (T
Pixel Port consists of the following inputs: Pixel Inputs: RED [A-H], BLUE [A-H], GREEN [A-H].
Output Delay is measured from the 50% rising edge of LOADIN to the 50% point of full-scale transition on the A pixel. t
Jitter is measured by triggering on the output clock, delayed by 15 s and then measuring the time period from the trigger edge to the next edge of the output clock
puts. Analog output load 10 pF. Databus (D7–D0) loaded as shown in Figure 1. Digital output load for SENSE 30 pF.
and internal gate transitions plus the pipeline stages delay. The output delay for pixels B-H will be the output delay to the A pixel (t
of clock cycles. Output rise/fall time is measured between the 10% and 90% points of full-scale transition. Settling time is measured from the 50% point of full-scale
transition to the output remaining within 1%. (Settling Time does not include clock and data feedthrough.)
after the delay. This measurement is repeated multiple times and the rms value is determined.
5% for all versions.
LOADIN Clocking Rate, f
LOADIN Cycle Time, t
LOADIN Low Time, t
LOADIN High Time, t
LOADIN to LOADOUT Delay, t
Pixel Setup Time, t
Pixel Hold Time, t
R/W, C0, C1 Setup Time, t
R/W, C0, C1 Hold Time, t
CE Low Time, t
CE High Time, t
CE Asserted to Data-Bus Driven, t
CE Asserted to Data-Bus Valid, t
CE Negated to Data-Bus Invalid, t
CE Negated to Data-Bus Three Stated, t
Write Data (D7–D0) Setup Time, t
Write Data (D7–D0) Hold Time, t
Analog Output Delay, t
Analog Output Rise/Fall Time, t
Analog Output Transition Time, t
RGB Analog Output Skew, t
Pipeline Delay, t
Jitter (1
MIN
9
PD
10
6
5
to T
5
6
2
MAX
3
17
1
), 0 C to +70 C.
LCLK
8
7
SK
18
12
4
19
13
11
16
(V
All specifications T
15
4
AA
2
= +5 V, V
14
TO OUTPUT PIN
Figure 1. LOADIN vs. Pixel Input Data
REF
Conditions
@ 360 MHz
(LOADIN = 45 MHz)
= +1.235 V, R
MIN
100pF
to T
MAX
3
–3–
unless otherwise noted.)
RSET
, R
GSET,
I
I
SINK
SOURCE
R
BSET
= 280
+2.1V
Min
10
16.67
6.67
6.67
1
4
10
10
25
25
2
1
10
10
, R
L
= 25
17
includes the analog delay due to DACs
Typ
5
0
2
2.5
0.5
5
5
0.8
25
19
55
for IOG, IOR, IOB, C
17
) plus the appropriate number
Max
45
20
15
1.5
ADV7129
L
= 10 pF.
MHz
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
ns
PCLKs
ps rms
Units