X9455_06 INTERSIL [Intersil Corporation], X9455_06 Datasheet - Page 15

• Manufacturer Part Number: X9455_06
• Description: Dual Two-wiper Digitally-Controlled Potentiometer
• Manufacturer: INTERSIL [Intersil Corporation]

Page Write Operation
As stated previously, the memory is organized as a single
Status Register (SR), and four pages of four registers each.
Each page contains one Data Register for each wiper.
Normally a page write operation will be used to efficiently
update all four Data Registers and WCR in a single Write
command. Note the special sequence for writing to a page:
First wiper 0A, then 1B, then 1A, then 0B as shown in Figure
9.
In order to perform a Page Write operation to the memory
array, the NVEnable bit in the SR must first be set to “1”.
A Page Write operation is initiated in the same manner as
the Byte Write operation; but instead of terminating the write
cycle after the first data byte is transferred, the master can
DR Level 0
DR Level 1
DR Level 2
DR Level 3
*Page writes may wrap around to the first address on a page from
the last address.
WCR
Signals from the
Signals from the
FIGURE 8. PAGE WRITE SEQUENCE*
Signal at SDA
WCR0A → WCR1B → WCR1A → WCR0B
DR0A0 → DR1B0 → DR1A0 →
DR0A1 → DR1B1 → DR1A1 →
DR0A2 → DR1B2 → DR1A2 →
DR0A3 → DR1B3 → DR1A3 →
Master
Slave
Signals from the
Signals from the
Signal at SDA
15
Master
Slave
S
a
t
r
t
0
1
0
Address
Slave
1
S
a
t
r
t
0
FIGURE 7. BYTE WRITE SEQUENCE
FIGURE 9. PAGE WRITE OPERATION
1
0
0
Write
Address
Slave
1
A
C
K
DR0B0
DR0B1
DR0B2
DR0B3
Address
0
Byte
Write
X9455
A
C
K
Address
transmit up to 4 bytes (See Figure 9). After the receipt of
each byte, the X9455 responds with an ACK, and the
internal WCR address is incremented by one. The page
address remains constant. When the address reaches the
end of the page, it “rolls over” and goes back to the first byte
of the same page.
For example, if the master writes three bytes to a page
starting at location DR1A2, the first two bytes are written to
locations DR1A2 and DR0B2, while the last byte is written to
location DR0A2. Afterwards, the WCR address would point
to location DR1B2. If the master supplies more than four
bytes of data, then new data overwrites the previous data,
one byte at a time.
The master terminates the loading of Data Bytes by issuing
a STOP condition, which initiates the nonvolatile write cycle.
As with the Byte Write operation, all inputs are disabled until
completion of the internal write cycle. If the WP pin is low,
the nonvolatile write cycle doesn’t start and the bytes are
discarded.
Notice that the Data Bytes are also written to the WCR of the
corresponding WCRs, therefore in the above example,
WCR1A, WCR0B, and WCR0A are also written, and
WCR1B is updated with the contents of DR1B2.
Byte
A
C
K
Data Byte (1)
A
C
K
2 < n < 4
Data
Byte
A
C
K
Data Byte (n)
A
C
K
S
o
p
t
A
C
K
S
o
p
t
July 28, 2006
FN8202.1