X9455_06 INTERSIL [Intersil Corporation], X9455_06 Datasheet - Page 9

• Manufacturer Part Number: X9455_06
• Description: Dual Two-wiper Digitally-Controlled Potentiometer
• Manufacturer: INTERSIL [Intersil Corporation]

Principles of Operation
The X9455 is an integrated circuit incorporating two resistor
arrays with dual wipers on each array, their associated
registers and counters, and the serial interface logic
providing direct communication between the host and the
digitally controlled potentiometers. This section provides
detail description of the following:
• Resistor Array
• Up/Down Interface
• 2-wire Interface
Resistor Array Description
The X9455 is comprised of two resistor arrays. Each array
contains 255 discrete resistive segments that are connected
in series. The physical ends of each array are equivalent to
the fixed terminals of a mechanical potentiometer (R
R
Each array has two independent wipers. At both ends of
each array and between each resistor segment are two
Li
inputs). (See Figure 1.)
“i” is either 0 or 1
DRiA0, DRiA1,
DRiB0, DRiB1,
Non-Volatile
Non-Volatile
DRiA2, and
DRiB2, and
Registers
Registers
DRiA3
DRiB3
Four
Data
Four
Data
9
FIGURE 1. DETAILED BLOCK DIAGRAM OF ONE DCP
Up/Down Interfaces
2-wire and
Register
Register
Counter
Counter
Volatile
WCRiA
Volatile
WCRiB
Wiper
Wiper
8-bit
8-bit
Hi
and
X9455
switches, one connected to each of the wiper pins (R
R
Within each individual array only one switch of each wiper
may be turned on at a time.
These switches are controlled by two Wiper Counter
Register (WCR). The 8-bits of the WCR are decoded to
select and enable one of 256 switches. Note that each wiper
has a dedicated WCR. When all bits of a WCR are zeroes,
the switch closest to the corresponding R
When all bits of a WCR are ones, the switch closest to the
corresponding R
The WCRs are volatile and may be written directly. There
are four non-volatile Data Registers (DR) associated with
each WCR. Each DR can be loaded into WCR. All DRs and
WCRs can be read or written.
Power Up and Down Requirements
During power up CS must be high to avoid inadvertant
“store” operations. At power up, the contents of Data
Registers Level 0 (DR0A0, DR0B0, DR1A0, and DR1B0),
are loaded into the corresponding wiper counter register.
WCRiA[7:0]
WCRiA[7:0]
WCRiB[7:0]
WCRiB[7:0]
WiB
Decoder
= FF hex
= 00 hex
= FF hex
= 00 hex
One of
256
).
255
254
255
254
1
0
.
.
.
.
.
.
1
0
H
pin is selected.
R
WiA
R
R
Hi
Li
L
pin is selected.
R
WiB
July 28, 2006
WiA
FN8202.1
and