XCR3032XL-10 XILINX [Xilinx, Inc], XCR3032XL-10 Datasheet - Page 8

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XCR3032XL-10

Manufacturer Part Number
XCR3032XL-10
Description
XCR3032XL 32 Macrocell CPLD
Manufacturer
XILINX [Xilinx, Inc]
Datasheet

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XCR3032XL 32 Macrocell CPLD
Revision History
The following table shows the revision history for this document.
8
02/05/01
04/19/01
08/27/01
01/08/02
06/27/02
11/18/00
04/11/01
Date
Version
1.0
1.1
1.2
1.3
1.4
1.5
1.6
Initial Xilinx release.
Removed Timing Model.
Update TSUF spec to meet UMC characterization data. Added Icc vs. Freq. numbers,
Table 1
I/O; changed V
Updated Typical I/V curve,
Changed from Advance to Preliminary; updated DC Electrical Characteristics; AC Electrical
Characteristics; Internal Timing Parameters; added Derating Curve; added -10 industrial
packages. Added 200 MHz to
to 0.5 ns.
Updated T
renamed T
to more closely resemble true test conditions, added note for T
measurement.Updated note 5 in AC Characteristics table lowering typical current draw
during configuration.
Added voltage and temperature to
adding T
and updated
PTCK
HI
SU
spec to correct a typo. Added single p-term setup time (T
to T
parameter to internal timing model.
OH
SU2
spec.
Figure
for setup time through the OR array. Updated AC Load Circuit diagram
www.xilinx.com
1-800-255-7778
Figure
1. Added Typical I/V curve,
Figure 1
2: added voltage levels.
Figure
and
Revision
2. Increased -5 T
Table
1. changed -5 F
Figure
Preliminary Product Specification
PCO
2; added
POD
to 6.0 (from 5.5 ns) by
SYSTEM
DS023 (v1.6) June 27, 2002
delay
SU1
Table
to 200 MHz, -5 T
) to AC Table,
2: Total User
F
R

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