ADSP-21266SKBC-2B AD [Analog Devices], ADSP-21266SKBC-2B Datasheet - Page 28
ADSP-21266SKBC-2B
Manufacturer Part Number
ADSP-21266SKBC-2B
Description
SHARC Embedded Processor
Manufacturer
AD [Analog Devices]
Datasheet
1.ADSP-21266SKBC-2B.pdf
(44 pages)
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ADSP-21266
Table 23. 16-Bit Memory Write Cycle
1
Parameter
Switching Characteristics
t
t
t
t
t
t
t
t
D = (data cycle duration) × t
H = t
On reset, ALE is an active high cycle. However, it can be reconfigured by software to be active low.
ALEW
ALERW
ADAS
ADAH
WW
ALEHZ
DWS
DWH
CCLK
(if a hold cycle is specified, else H = 0)
ALE Pulse Width
ALE Deasserted to Read/Write Asserted
Address/Data 15–0 Setup Before ALE Deasserted
Address/Data 15–0 Hold After ALE Deasserted
WR Pulse Width
ALE Deasserted
Address/Data 15–0 Setup Before WR High
Address/Data 15–0 Hold After WR High
AD15-0
ALE
WR
RD
CCLK
1
to Address/Data 15–0 In High Z
VALID ADDRESS
t
ADAS
t
ALEW
Figure 20. 16-Bit Memory Write Cycle
Rev. B | Page 28 of 44 | May 2005
t
ADAH
t
ALEH
t
ALERW
1
1
t
t
DWS
VALID DATA
WW
Min
2 × t
1 × t
2.5 × t
0.5 × t
D – 2
0.5 × t
D
0.5 × t
CCLK
CCLK
CCLK
CCLK
CCLK
CCLK
– 2
– 0.5
t
DWH
– 2.0
– 0.8
– 0.8
– 1.5 + H
Max
0.5t
CCLK
+ 2.0
Unit
ns
ns
ns
ns
ns
ns
ns
ns
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