PIC12CE673 MICROCHIP [Microchip Technology], PIC12CE673 Datasheet
PIC12CE673
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PIC12CE673 Summary of contents
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... Operating speed MHz clock input DC - 400 ns instruction cycle Memory Device Data Program RAM PIC12CE673 1024 x 14 128 x 8 PIC12CE674 2048 x 14 128 x 8 • 14-bit wide instructions • 8-bit wide data path • Interrupt capability • Special function hardware registers • ...
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PIC12CE67X Table of Contents 1.0 General Description ....................................................................................................................................................................... 3 2.0 PIC12CE67X Device Varieties....................................................................................................................................................... 5 3.0 Architectural Overview ................................................................................................................................................................... 7 4.0 Memory Organization................................................................................................................................................................... 11 5.0 I/O Port......................................................................................................................................................................................... 25 6.0 EEPROM Peripheral Operation ................................................................................................................................................... 27 7.0 Timer0 Module ............................................................................................................................................................................. 31 8.0 Analog-to-Digital ...
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GENERAL DESCRIPTION The PIC12CE67X devices are low-cost, high-perfor- mance, CMOS, fully-static, 8-bit microcontroller with integrated analog-to-digital (A/D) EEPROM data memory in the PIC12CEXXX Micro- controller family. All PICmicro™ microcontrollers employ an advanced RISC architecture. The PIC12C67X microcontrollers have enhanced ...
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... JW, SOIC All PIC12CXXX & PIC12CEXXX devices have Power-on Reset, selectable Watchdog Timer, selectable code protect and high I/O current capability. All PIC12CXXX & PIC12CEXXX devices use serial programming with data pin GP0 and clock pin GP1. DS40181B-page 4 PIC12C672 PIC12CE673 PIC12CE674 ...
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PIC12CE67X DEVICE VARIETIES A variety of frequency ranges and packaging options are available. Depending on application and production requirements, the proper device option can be selected using the information in the PIC12CE67X Product Iden- tification System section at the ...
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PIC12CE67X NOTES: DS40181B-page 6 Preliminary 1998 Microchip Technology Inc. ...
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... PIC12CE67X device. RAM Program Device Data Memory Memory PIC12CE673 128 x 8 PIC12CE674 128 x 8 1998 Microchip Technology Inc. The PIC12CE67X can directly or indirectly address its register files or data memory. All special function regis- ters, including the program counter, are mapped in the data memory ...
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... PIC12CE67X FIGURE 3-1: PIC12CE67X BLOCK DIAGRAM Device Program Memory Data Memory (RAM) PIC12CE673 PIC12CE674 EPROM Program Memory Program 14 Bus Instruction reg Direct Addr 8 Instruction Decode & Start-up Timer Control Timing OSC1/CLKIN Generation OSC2/CLKOUT Internal 4 MHz Clock MCLR Note 1: Higher order bits are from the STATUS register. ...
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TABLE 3-1: PIC12CE67X PINOUT DESCRIPTION DIP Pin Name # GP0/AN0 7 GP1/AN1/V 6 REF GP2/T0CKI/AN2/INT 5 GP3/MCLR GP4/OSC2/AN3/ 3 CLKOUT GP5/OSC1/CLKIN Legend input output, I/O = input/output, ...
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PIC12CE67X 3.1 Clocking Scheme/Instruction Cycle The clock input (from OSC1) is internally divided by four to generate four non-overlapping quadrature clocks namely Q1, Q2, Q3 and Q4. Internally, the pro- gram counter (PC) is incremented every Q1, the instruction is ...
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... Program Memory Organization The PIC12CE67X has a 13-bit program counter capa- ble of addressing program memory space. For the PIC12CE673 the first (0000h-03FFh) is implemented. For the PIC12CE674, the first (0000h-07FFh) is implemented. Accessing a location above the physi- cally implemented address will cause a wraparound. ...
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PIC12CE67X FIGURE 4-2: PIC12CE67X REGISTER FILE MAP File Address (1) 00h INDF INDF 01h TMR0 OPTION 02h PCL PCL 03h STATUS STATUS 04h FSR FSR 05h GPIO TRIS 06h 07h 08h 09h 0Ah PCLATH PCLATH 0Bh INTCON INTCON 0Ch PIR1 ...
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TABLE 4-1: PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY Address Name Bit 7 Bit 6 Bank 0 (1) 00h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 01h TMR0 Timer0 module’s register (1) 02h ...
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PIC12CE67X TABLE 4-1: PIC12CE67X SPECIAL FUNCTION REGISTER SUMMARY (CONT.) Address Name Bit 7 Bit 6 Bank 1 (1) 80h INDF Addressing this location uses contents of FSR to address data memory (not a physical register) 81h OPTION GPPU INTEDG (1) ...
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STATUS REGISTER The STATUS register, shown in Figure 4-3, contains the arithmetic status of the ALU, the RESET status and the bank select bits for data memory. The STATUS register can be the destination for any instruction, as with ...
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PIC12CE67X 4.2.2.2 OPTION REGISTER The OPTION register is a readable and writable regis- ter which contains various control bits to configure the TMR0/WDT prescaler, the External INT Interrupt, TMR0, and the weak pull-ups on GPIO. FIGURE 4-4: OPTION REGISTER (ADDRESS ...
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INTCON REGISTER The INTCON Register is a readable and writable regis- ter which contains various enable and flag bits for the TMR0 register overflow, GPIO Port change and Exter- nal GP2/INT Pin interrupts. FIGURE 4-5: INTCON REGISTER (ADDRESS 0Bh, ...
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PIC12CE67X 4.2.2.4 PIE1 REGISTER This register contains the individual enable bits for the Peripheral interrupts. FIGURE 4-6: PIE1 REGISTER (ADDRESS 8Ch) U-0 R/W-0 U-0 U-0 — ADIE — — bit7 bit 7: Unimplemented: Read as '0' bit 6: ADIE: A/D ...
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PIR1 REGISTER This register contains the individual flag bits for the Peripheral interrupts. FIGURE 4-7: PIR1 REGISTER (ADDRESS 0Ch) U-0 R/W-0 U-0 U-0 — ADIF — — bit7 bit 7: Unimplemented: Read as '0' bit 6: ADIF: A/D Converter ...
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PIC12CE67X 4.2.2.6 PCON REGISTER The Power Control (PCON) register contains a flag bit to allow differentiation between a Power-on Reset (POR), an external MCLR Reset, and WDT Reset. FIGURE 4-8: PCON REGISTER (ADDRESS 8Eh) U-0 U-0 U-0 U-0 — — ...
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OSCCAL REGISTER The Oscillator Calibration (OSCCAL) register is used to calibrate the internal 4 MHz oscillator. It contains six bits for calibration. Increasing the cal value increases the frequency. FIGURE 4-9: OSCCAL REGISTER (ADDRESS 8Fh) R/W-1 R/W-0 R/W-0 R/W-0 ...
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PIC12CE67X 4.3 PCL and PCLATH The program counter (PC) is 13-bits wide. The low byte comes from the PCL register, which is a readable and writable register. The high byte (PC<12:8>) is not directly readable or writable and comes from ...
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Indirect Addressing, INDF and FSR Registers The INDF register is not a physical register. Addressing the INDF register will cause indirect addressing. Indirect addressing is possible by using the INDF reg- ister. Any instruction using the INDF register actually ...
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PIC12CE67X NOTES: DS40181B-page 24 Preliminary 1998 Microchip Technology Inc. ...
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I/O PORT As with any other register, the I/O register can be written and read under program control. However, read instructions (e.g., MOVF GPIO,W) always read the I/O pins independent of the pin’s input/output modes. On RESET, all I/O ...
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PIC12CE67X TABLE 5-1: SUMMARY OF PORT REGISTERS Address Name Bit 7 Bit 6 85h TRIS — — 81h OPTION GPPU INTEDG (1) 03h STATUS IRP RP1 05h GPIO SCL SDA Legend: Shaded cells not used by Port Registers, read as ...
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... EEPROM PERIPHERAL OPERATION The PIC12CE673 and PIC12CE674 each have 16 bytes of EEPROM data memory. The EEPROM mem- ory has an endurance of 1,000,000 erase/write cycles and a data retention of greater than 40 years. The EEPROM data memory supports a bi-directional 2-wire bus and data transmission protocol. These two-wires ...
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PIC12CE67X FIGURE 6-1: DATA TRANSFER SEQUENCE ON THE SERIAL BUS (A) (B) SCL SDA START CONDITION FIGURE 6-2: ACKNOWLEDGE TIMING SCL SDA Data from transmitter Transmitter must release the SDA line at this point allowing the ...
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WRITE OPERATIONS 6.3.1 BYTE WRITE Following the start signal from the processor, the device code (4 bits), the don't care bits (3 bits), and the R/W bit (which is a logic low) are placed onto the bus by the ...
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PIC12CE67X 6.5 READ OPERATIONS Read operations are initiated in the same way as write operations with the exception that the R/W bit of the EEPROM address is set to one. There are three basic types of read operations: current address ...
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TIMER0 MODULE The Timer0 module timer/counter has the following fea- tures: • 8-bit timer/counter • Readable and writable • 8-bit software programmable prescaler • Internal or external clock select • Interrupt on overflow from FFh to 00h • Edge ...
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PIC12CE67X FIGURE 7-3: TIMER0 TIMING: INTERNAL CLOCK/PRESCALE 1 ...
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Using Timer0 with an External Clock When an external clock input is used for Timer0, it must meet certain requirements. The requirements ensure the external clock can be synchronized with the internal phase clock (T ). Also, there is ...
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PIC12CE67X 7.3 Prescaler An 8-bit counter is available as a prescaler for the Timer0 module postscaler for the Watchdog Timer, respectively (Figure 7-6). For simplicity, this counter is being referred to as “prescaler” throughout this data sheet. ...
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SWITCHING PRESCALER ASSIGNMENT The prescaler assignment is fully under software con- trol, i.e., it can be changed “on the fly” during program execution. Note: To avoid an unintended device RESET, the following instruction sequence (shown in Example 7-1) must ...
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PIC12CE67X NOTES: DS40181B-page 36 Preliminary 1998 Microchip Technology Inc. ...
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ANALOG-TO-DIGITAL CONVERTER (A/D) MODULE The analog-to-digital (A/D) converter module has four analog inputs. The A/D allows conversion of an analog input signal to a corresponding 8-bit digital number (refer to Applica- tion Note AN546 for use of A/D Converter). ...
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PIC12CE67X FIGURE 8-2: ADCON1 REGISTER (ADDRESS 9Fh) U-0 U-0 U-0 U-0 — — — — bit7 bit 7-2: Unimplemented: Read as '0' bit 1-0: PCFG2:PCFG0: A/D Port Configuration Control bits PCFG2:PCFG0 GP4 (1) A 000 A 001 D 010 D ...
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The ADRES register contains the result of the A/D con- version. When the A/D conversion is complete, the result is loaded into the ADRES register, the GO/DONE bit (ADCON0<2>) is cleared, and A/D interrupt flag bit ADIF (PIE1<6>) is set. ...
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PIC12CE67X 8.1 A/D Sampling Requirements For the A/D converter to meet its specified accuracy, the charge holding capacitor (C ) must be allowed HOLD to fully charge to the input channel voltage level. The analog input model is shown in ...
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Selecting the A/D Conversion Clock The A/D conversion time per bit is defined as T A/D conversion requires 9.5 T per 8-bit conversion. AD The source of the A/D conversion clock is software selected. The four possible options for ...
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PIC12CE67X 8.4 A/D Conversions Example 8-2 show how to perform an A/D conversion. The GP pins are configured as analog inputs. The ana- log reference ( the device V REF DD rupt is enabled, and the A/D conversion ...
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A/D Operation During Sleep The A/D module can operate during SLEEP mode. This requires that the A/D clock source be set to RC (ADCS1:ADCS0 = 11). When the RC clock source is selected, the A/D module waits one instruction ...
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PIC12CE67X FIGURE 8-6: FLOWCHART OF A/D OPERATION ADON = 0 Yes ADON = 0? No Acquire Selected Channel Yes Yes Start of A/D A/D Clock Conversion Delayed = RC? 1 Instruction Cycle No Yes Abort Conversion ...
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... CP0 MCLRE bit13 bit 13-8, CP1:CP0: Code Protection bit pairs 6- Code protection off 10 = Locations 400h through 7FEh code protected (do not use for PIC12CE673 Locations 200h through 7FEh code protected 00 = All memory is code protected bit 7: MCLRE: Master Clear Reset Enable bit 1 = Master Clear Enabled ...
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PIC12CE67X 9.2 Oscillator Configurations 9.2.1 OSCILLATOR TYPES The PIC12CE67X can be operated in seven different oscillator modes. The user can program three configuration bits (FOSC2:FOSC0) to select one of these seven modes: • LP: Low Power Crystal • HS: High ...
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EXTERNAL CRYSTAL OSCILLATOR CIRCUIT Either a prepackaged oscillator or a simple oscillator circuit with TTL gates can be used as an external crystal oscillator circuit. Prepackaged oscillators provide a wide operating range and better stability. A well-designed crystal oscillator ...
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... XX is the calibration value. In order to retrieve the cali- bration value, issue a CALL YY instruction where YY is the last location in program memory (03FFh for the PIC12CE673, 07FFh for the PIC12CE674). Control will be returned to the user’s program with the calibration value loaded into the W register. The program should then perform a MOVWF OSCCAL instruction to load the value into the internal RC oscillator trim register ...
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FIGURE 9-7: SIMPLIFIED BLOCK DIAGRAM OF ON-CHIP RESET CIRCUIT Weak Pull-up GP3/MCLR/V Pin PP WDT SLEEP Module WDT Time-out V rise DD detect Power-on Reset V DD OST/PWRT OST 10-bit Ripple-counter OSC1/ CLKIN Pin PWRT (1) On-chip 10-bit Ripple-counter RC ...
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PIC12CE67X 9.4 Power-on Reset (POR), Power-up Timer (PWRT) and Oscillator Start-up Timer (OST) 9.4.1 POWER-ON RESET (POR) The on-chip POR circuit holds the chip in reset until V has reached a high enough level for proper opera- DD tion. To ...
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TABLE 9-5: RESET CONDITION FOR SPECIAL REGISTERS Condition Power-on Reset MCLR Reset during normal operation MCLR Reset during SLEEP WDT Reset during normal operation WDT Wake-up from SLEEP Interrupt wake-up from SLEEP Legend unchanged unknown, - ...
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PIC12CE67X FIGURE 9-8: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT TIME-OUT OST TIME-OUT INTERNAL RESET FIGURE 9-9: TIME-OUT SEQUENCE ON POWER-UP (MCLR NOT TIED MCLR INTERNAL POR PWRT ...
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FIGURE 9-11: EXTERNAL POWER-ON RESET CIRCUIT (FOR SLOW V POWER-UP MCLR PIC12CE67X C Note 1: External Power-on Reset circuit is required only if V power-up slope is too slow. The DD diode D helps ...
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PIC12CE67X 9.5 Interrupts There are four sources of interrupt: Interrupt Sources TMR0 overflow interrupt External interrupt GP2/INT pin GPIO Port change interrupts (pins GP0, GP1, GP3) A/D Interrupt The interrupt control register (INTCON) records individ- ual interrupt requests in flag ...
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FIGURE 9-15: INT PIN INTERRUPT TIMING OSC1 CLKOUT 3 4 INT pin 1 INTF flag 5 (INTCON<1>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC Instruction Inst (PC) fetched Instruction Inst (PC-1) executed Note 1: INTF ...
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PIC12CE67X 9.5.1 TMR0 INTERRUPT An overflow (FFh 00h) in the TMR0 register will set flag bit T0IF (INTCON<2>). The interrupt can be enabled/disabled by setting/clearing enable bit T0IE (INTCON<5>). (Section 7.0) 9.5.2 INT INTERRUPT External interrupt on GP2/INT pin is ...
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Watchdog Timer (WDT) The Watchdog Timer is a free running on-chip RC oscil- lator which does not require any external components. This RC oscillator is separate from the RC oscillator of the OSC1/CLKIN pin. That means that the WDT ...
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PIC12CE67X 9.8 Power-down Mode (SLEEP) Power-down mode is entered by executing a SLEEP instruction. If enabled, the Watchdog Timer will be cleared but keeps running, the PD bit (STATUS<3>) is cleared, the TO (STATUS<4>) bit is set, and the oscillator ...
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FIGURE 9-18: WAKE-UP FROM SLEEP THROUGH INTERRUPT OSC1 CLKOUT(4) GPIO pin GPIF flag (INTCON<0>) GIE bit (INTCON<7>) INSTRUCTION FLOW PC PC PC+1 Instruction Inst( Inst(PC) = SLEEP fetched Instruction SLEEP ...
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PIC12CE67X NOTES: DS40181B-page 60 Preliminary 1998 Microchip Technology Inc. ...
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INSTRUCTION SET SUMMARY Each PIC12CE67X instruction is a 14-bit word divided into an OPCODE which specifies the instruction type and one or more operands which further specify the operation of the instruction. The PIC12CE67X instruc- tion set summary in ...
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PIC12CE67X 10.1 Special Function Registers as Source/Destination The PIC12CE67X’s orthogonal instruction set allows read and write of all file registers, including special function registers. There are some special situations the user should be aware of: 10.1.1 STATUS AS DESTINATION If ...
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TABLE 10-2: INSTRUCTION SET SUMMARY Mnemonic, Description Operands BYTE-ORIENTED FILE REGISTER OPERATIONS ADDWF f, d Add W and f ANDWF f, d AND W with f CLRF f Clear f CLRW - Clear W COMF f, d Complement f DECF ...
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PIC12CE67X 10.2 Instruction Descriptions ADDLW Add Literal and W [ label ] ADDLW Syntax: Operands 255 Operation: ( (W) Status Affected: C, DC, Z Encoding: 11 111x Description: The contents of the W register are added ...
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BCF Bit Clear f Syntax: [ label ] BCF f,b Operands 127 Operation: 0 (f<b>) Status Affected: None Encoding: 01 00bb Description: Bit 'b' in register 'f' is cleared Words: 1 Cycles: 1 Example BCF ...
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PIC12CE67X BTFSS Bit Test f, Skip if Set Syntax: [ label ] BTFSS f,b Operands 127 0 b < 7 Operation: skip if (f<b> Status Affected: None Encoding: 01 11bb Description: If bit 'b' in register ...
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CLRWDT Clear Watchdog Timer Syntax: [ label ] CLRWDT Operands: None Operation: 00h WDT 0 WDT prescaler Status Affected: TO, PD Encoding: 00 0000 Description: CLRWDT instruction resets the Watch- dog Timer. It also resets the ...
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PIC12CE67X GOTO Unconditional Branch Syntax: [ label ] GOTO k Operands 2047 Operation: k PC<10:0> PCLATH<4:3> PC<12:11> Status Affected: None Encoding: 10 1kkk Description: GOTO is an unconditional branch. The eleven bit immediate value is loaded into PC ...
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IORWF Inclusive OR W with f Syntax: [ label ] IORWF Operands 127 d [0,1] Operation: (W) .OR. (f) (dest) Status Affected: Z Encoding: 00 0100 Description: Inclusive OR the W register with regis- ter 'f'. If 'd' ...
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PIC12CE67X NOP No Operation Syntax: [ label ] NOP Operands: None Operation: No operation Status Affected: None Encoding: 00 0000 Description: No operation. Words: 1 Cycles: 1 Example NOP OPTION Load Option Register Syntax: [ label ] OPTION Operands: None ...
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RETURN Return from Subroutine Syntax: [ label ] RETURN Operands: None Operation: TOS PC Status Affected: None Encoding: 00 0000 Description: Return from subroutine. The stack is POPed and the top of the stack (TOS) is loaded into the program ...
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PIC12CE67X SUBLW Subtract W from Literal Syntax: [ label ] SUBLW k Operands 255 Operation (W) W) Status C, DC, Z Affected: Encoding: 11 110x kkkk Description: The W register is subtracted (2’s com- plement method) ...
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SWAPF Swap Nibbles in f Syntax: [ label ] SWAPF f,d Operands 127 d [0,1] Operation: (f<3:0>) (dest<7:4>), (f<7:4>) (dest<3:0>) Status Affected: None Encoding: 00 1110 Description: The upper and lower nibbles of regis- ter 'f' are exchanged. ...
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PIC12CE67X NOTES: DS40181B-page 74 Preliminary 1998 Microchip Technology Inc. ...
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DEVELOPMENT SUPPORT 11.1 Development Tools The PICmicr microcontrollers are supported with a full range of hardware and software development tools: • MPLAB™-ICE Real-Time In-Circuit Emulator • ICEPIC Low-Cost PIC16C5X and PIC16CXXX In-Circuit Emulator • PRO MATE II Universal Programmer ...
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PIC12CE67X 11.6 SIMICE Entry-Level Hardware Simulator SIMICE is an entry-level hardware development sys- tem designed to operate in a PC-based environment with Microchip’s simulator MPLAB™-SIM. Both SIM- ICE and MPLAB-SIM run under Microchip Technol- ogy’s MPLAB Integrated Development Environment (IDE) ...
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MPLAB Integrated Development Environment Software The MPLAB IDE Software brings an ease of software development previously unseen in the 8-bit microcon- troller market. MPLAB is a windows based application which contains: • A full featured editor • Three operating ...
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PIC12CE67X 11. Evaluation and EE OQ Programming Tools K L evaluation and programming tools support EE OQ Microchips HCS Secure Data Products. The HCS eval- uation kit includes an LCD display to show changing codes, a decoder to ...
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PIC12C5XX PIC14000 PIC16C5X PIC16CXXX PIC16C6X PIC16C7XX PIC16C8X PIC16C9XX PIC17C4X PIC17C7XX ü ü ü MPLAB™-ICE ICEPIC Low-Cost ü In-Circuit Emulator MPLAB Integrated ü ü ü Development Environment MPLAB C17* Compiler fuzzy TECH -MP Explorer/Edition ü ü ü Fuzzy Logic Dev. Tool ...
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PIC12CE67X NOTES: DS40181B-page 80 Preliminary 1998 Microchip Technology Inc. ...
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ELECTRICAL CHARACTERISTICS FOR PIC12CE67X Absolute Maximum Ratings † Ambient temperature under bias............................................................................................................. .–40 to +125 C Storage temperature ............................................................................................................................. – +150 C Voltage on any pin with respect Voltage on V with respect to ...
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... Freq: 200 kHz max. The shaded sections indicate oscillator selections which are tested for functionality, but not for MIN/MAX specifications recommended that the user select the device type that ensures the specifications required. PIC12LCE673-04 PIC12CE673/JW PIC12LCE674-04 PIC12CE674/ 2. ...
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... DC Characteristics: PIC12CE673-04 (Commercial, Industrial, Extended PIC12CE673-10 (Commercial, Industrial, Extended PIC12CE674-04 (Commercial, Industrial, Extended PIC12CE674-10 (Commercial, Industrial, Extended DC CHARACTERISTICS Parm Characteristic No. D001 Supply Voltage D001A D002 RAM Data Retention Voltage (Note 1) D003 V start voltage to DD ensure internal Power-on Reset signal D004 V rise rate to ensure inter- ...
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PIC12CE67X 12.2 DC Characteristics: PIC12LCE673-04 (Commercial, Industrial) PIC12LCE674-04 (Commercial, Industrial) DC CHARACTERISTICS Param Characteristic Sym No. D001 Supply Voltage V DD D002* RAM Data Retention V DR Voltage (Note 1) D003 V start voltage POR ensure internal ...
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... DC Characteristics: PIC12CE673-04 (Commercial, Industrial, Extended PIC12CE673-10 (Commercial, Industrial, Extended PIC12CE674-04 (Commercial, Industrial, Extended PIC12CE674-10 (Commercial, Industrial, Extended DC CHARACTERISTICS Param Characteristic No. Input Low Voltage I/O ports D030 with TTL buffer D031 with Schmitt Trigger buffer D032 MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) D033 OSC1 (in XT, HS and LP) ...
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PIC12CE67X DC CHARACTERISTICS Param Characteristic No. Output High Voltage D090 I/O ports/CLKOUT (Note 3) D090A D092 OSC2 D092A Capacitive Loading Specs on Output Pins D100 OSC2 pin D101 All I/O pins and OSC2 † Data in “Typ” column is at ...
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DC Characteristics: PIC12LCE671-04 (Commercial, Industrial) PIC12LCE672-04 (Commercial, Industrial) DC CHARACTERISTICS Param Characteristic No. Input Low Voltage I/O ports D030 with TTL buffer D031 with Schmitt Trigger buffer D032 MCLR, GP2/T0CKI/AN2/INT (in EXTRC mode) D033 OSC1 (in XT, HS and ...
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PIC12CE67X DC CHARACTERISTICS Param Characteristic No. Capacitive Loading Specs on Output Pins D100 OSC2 pin D101 All I/O pins and OSC2 † Data in “Typ” column unless otherwise stated. These parameters are for design guidance ...
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Timing Parameter Symbology The timing parameter symbols have been created following one of the following formats: 1. TppS2ppS 2. TppS T F Frequency Lowercase letters (pp) and their meanings CCP1 ck CLKOUT SDI do ...
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PIC12CE67X 12.6 Timing Diagrams and Specifications FIGURE 12-2: EXTERNAL CLOCK TIMING Q4 OSC1 CLKOUT TABLE 12-2: CLOCK TIMING REQUIREMENTS Parameter Sym Characteristic No. Fosc External CLKIN Frequency (Note 1) Oscillator Frequency (Note 1) 1 Tosc External CLKIN Period (Note 1) ...
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TABLE 12-3: CALIBRATED INTERNAL RC FREQUENCIES - PIC12C508/C509 AC Characteristics Standard Operating Conditions (unless otherwise specified) Operating Temperature Operating Voltage V Parameter Sym No. Internal Calibrated RC Internal Calibrated RC * These parameters are characterized but not tested. Note 1: ...
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PIC12CE67X FIGURE 12-3: CLKOUT AND I/O TIMING Q4 OSC1 CLKOUT I/O Pin (input) I/O Pin old value (output) Note: Refer to Figure 12-1 for load conditions. TABLE 12-4: CLKOUT AND I/O TIMING REQUIREMENTS Parameter Sym Characteristic No. 10* TosH2ckL OSC1 ...
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FIGURE 12-4: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, AND POWER-UP TIMER TIMING V DD MCLR Internal POR 33 PWRT Timeout 32 OSC Timeout Internal RESET Watchdog Timer RESET I/O Pins TABLE 12-5: RESET, WATCHDOG TIMER, OSCILLATOR START-UP TIMER, POWER-UP TIMER ...
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PIC12CE67X FIGURE 12-5: TIMER0 CLOCK TIMINGS GP2/T0CKI TMR0 Note: Refer to Figure 12-1 for load conditions. TABLE 12-6: TIMER0 CLOCK REQUIREMENTS Param Sym Characteristic No. 40 Tt0H T0CKI High Pulse Width 41 Tt0L T0CKI Low Pulse Width 42 Tt0P T0CKI ...
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... TABLE 12-8: A/D CONVERTER CHARACTERISTICS: PIC12CE673-04 (COMMERCIAL, INDUSTRIAL, EXTENDED PIC12CE673-10 (COMMERCIAL, INDUSTRIAL, EXTENDED PIC12CE674-04 (COMMERCIAL, INDUSTRIAL, EXTENDED PIC12CE674-10 (COMMERCIAL, INDUSTRIAL, EXTENDED Parameter Sym Characteristic No. N Resolution R N Integral error INT N Differential error DIF N Full scale error FS N Offset error OFF — Monotonicity V Reference voltage ...
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PIC12CE67X TABLE 12-9: A/D CONVERTER CHARACTERISTICS: PIC12LCE673-04 (COMMERCIAL, INDUSTRIAL) PIC12LCE674-04 (COMMERCIAL, INDUSTRIAL) Parameter Sym Characteristic No. N Resolution R N Integral error INT N Differential error DIF N Full scale error FS N Offset error OFF — Monotonicity V Reference ...
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FIGURE 12-6: A/D CONVERSION TIMING BSF ADCON0 /2) OSC Q4 132 A/D CLK A/D DATA ADRES ADIF GO SAMPLE Note 1: If the A/D clock source is selected as RC, a time of T SLEEP instruction to be ...
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PIC12CE67X NOTES: DS40181B-page 98 Preliminary 1998 Microchip Technology Inc. ...
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DC AND AC CHARACTERISTICS - PIC12CE67X The graphs and tables provided in this section are for design guidance and are not tested. In some graphs or tables the data presented are outside specified operating range (e.g., outside specified V ...
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PIC12CE67X TABLE 13-1: DYNAMIC I (TYPICAL) - WDT ENABLED Oscillator Frequency External RC Internal *Does not include current through external R&C. FIGURE 13-3: WDT TIMER TIME-OUT PERIOD vs ...
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FIGURE 13- 500m 1.0 1.5 2.0 V (Volts) OH FIGURE 13- ...
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PIC12CE67X FIGURE 13- -10 -15 -20 -25 -30 3.5 4.0 4.5 V (Volts) OH DS40181B-page 102 FIGURE 13- 5.0 5.5 0 ...
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PACKAGING INFORMATION 14.1 Package Marking Information 8-Lead PDIP (300 mil) MMMMMMMM XXXXXCDE AABB 8-Lead Windowed Ceramic Side Brazed (300 mil) MM MMMMMM Legend: MM...M Microchip part number information XX...X Customer specific information* AA Year code (last 2 digits of ...
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PIC12CE67X Package Type: K04-018 8-Lead Plastic Dual In-line (P) – 300 mil Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Shoulder Radius Lead Thickness Top to Seating ...
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Package Type: K04-084 8-Lead Ceramic Side Brazed Dual In-line with Window (JW) – 300 mil Units Dimension Limits PCB Row Spacing Number of Pins Pitch Lower Lead Width Upper Lead Width Lead Thickness Top to ...
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PIC12CE67X NOTES: DS40181B-page 106 Preliminary 1998 Microchip Technology Inc. ...
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... Changing Prescaler (Timer0 to WDT) ........................ 35 Changing Prescaler (WDT to Timer0) ........................ 35 Indirect Addressing..................................................... 23 Code Protection ............................................................ 45, 59 COMF Instruction ............................................................... 67 Computed GOTO ............................................................... 22 Configuration Bits ............................................................... bit.................................................................................. 15 DC Characteristics PIC12CE673............................................................... 83 PIC12CE674............................................................... 83 DECF Instruction ................................................................ 67 DECFSZ Instruction............................................................ 67 Development Support ..................................................... 3, 75 Development Tools............................................................. 75 Diagrams - See Block Diagrams Digit Carry bit .........................................................................7 Direct Addressing ............................................................... 23 E EEPROM Peripheral Operation ...
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PIC12CE67X ANDLW ....................................................................... 64 ANDWF ....................................................................... 64 BCF ............................................................................. 65 BSF ............................................................................. 65 BTFSC ........................................................................ 65 BTFSS ........................................................................ 66 CALL ........................................................................... 66 CLRF........................................................................... 66 CLRW ......................................................................... 66 CLRWDT..................................................................... 67 COMF ......................................................................... 67 DECF .......................................................................... 67 DECFSZ...................................................................... 67 GOTO ......................................................................... 68 ...
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PS2 bit ................................................................................ 16 PSA bit ................................................................................ 16 PUSH .................................................................................. Oscillator ....................................................................... 47 Read Modify Write .............................................................. 26 Read-Modify-Write .............................................................. 26 Register File........................................................................ 11 Registers Map PIC12CE67X ...................................................... 12 Reset Conditions......................................................... 51 Reset............................................................................. 45, 48 Reset Conditions ...
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PIC12CE67X DS40181B-page 110 Preliminary 1998 Microchip Technology Inc. ...
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ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web (WWW) site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must ...
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PIC12CE67X READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which ...
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... C to +125 MHz/200 kHz MHz PIC12CE673 PIC12CE674 PIC12LCE673 PIC12LCE674 Preliminary PIC12CE67X Examples a) PIC12CE673-04/P Commercial Temp., PDIP Package, 4 MHz, normal V limits DD b) PIC12CE673-04I/P Industrial Temp., PDIP package, 4 MHz, normal V limits DD c) PIC12CE673-10I/P Industrial Temp., PDIP package, 10 MHz, normal V limits DD DS40181B-page 113 ...
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PIC12CE67X NOTES: DS40181B-page 114 Preliminary 1998 Microchip Technology Inc. ...
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NOTES: 1998 Microchip Technology Inc. PIC12CE67X Preliminary DS40181B-page 115 ...
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M W ORLDWIDE AMERICAS Corporate Office Microchip Technology Inc. 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 602-786-7200 Fax: 602-786-7277 Technical Support: 602 786-7627 Web: http://www.microchip.com Atlanta Microchip Technology Inc. 500 Sugar Mill Road, Suite 200B Atlanta, GA 30350 Tel: ...