PIC12CE673 MICROCHIP [Microchip Technology], PIC12CE673 Datasheet - Page 54

• Manufacturer Part Number: PIC12CE673
• Description: 8-Pin, 8-Bit CMOS Microcontroller with A/D Converter and EEPROM Data Memory
• Manufacturer: MICROCHIP [Microchip Technology]

PIC12CE67X
9.5
There are four sources of interrupt:
The interrupt control register (INTCON) records individ-
ual interrupt requests in flag bits. It also has individual
and global interrupt enable bits.
A global interrupt enable bit, GIE (INTCON<7>)
enables (if set) all un-masked interrupts or disables (if
cleared) all interrupts. When bit GIE is enabled, and an
interrupt’s flag bit and mask bit are set, the interrupt will
vector immediately. Individual interrupts can be dis-
abled through their corresponding enable bits in vari-
ous registers. Individual interrupt bits are set
regardless of the status of the GIE bit. The GIE bit is
cleared on reset.
FIGURE 9-14: INTERRUPT LOGIC
DS40181B-page 54
TMR0 overflow interrupt
External interrupt GP2/INT pin
GPIO Port change interrupts (pins GP0, GP1, GP3)
A/D Interrupt
Note:
Interrupts
Individual interrupt flag bits are set regard-
less of the status of their corresponding
mask bit or the GIE bit.
Interrupt Sources
ADIF
ADIE
INTF
INTE
T0IF
T0IE
GPIF
GPIE
PEIE
GIE
Preliminary
The “return from interrupt” instruction, RETFIE, exits
the interrupt routine as well as sets the GIE bit, which
re-enables interrupts.
The GP2/INT, GPIO port change interrupt and the
TMR0 overflow interrupt flags are contained in the
INTCON register.
The peripheral interrupt flag ADIF, is contained in the
special function register PIR1. The corresponding
interrupt enable bit is contained in special function reg-
ister PIE1, and the peripheral interrupt enable bit is
contained in special function register INTCON.
When an interrupt is responded to, the GIE bit is
cleared to disable any further interrupt, the return
address is pushed onto the stack and the PC is loaded
with 0004h. Once in the interrupt service routine the
source(s) of the interrupt can be determined by polling
the interrupt flag bits. The interrupt flag bit(s) must be
cleared in software before re-enabling interrupts to
avoid recursive interrupts.
For external interrupt events, such as GPIO change
interrupt, the interrupt latency will be three or four
instruction cycles. The exact latency depends when the
interrupt event occurs (Figure 8-15). The latency is the
same for one or two cycle instructions. Individual inter-
rupt flag bits are set regardless of the status of their
corresponding mask bit or the GIE bit.
Wakeup
(If in SLEEP mode)
Interrupt to CPU
1998 Microchip Technology Inc.