SAB-C161K-L16M SIEMENS [Siemens Semiconductor Group], SAB-C161K-L16M Datasheet
SAB-C161K-L16M
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SAB-C161K-L16M Summary of contents
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Microcomputer Components 16-Bit CMOS Single-Chip Microcontroller C161V/C161K/C161O Data Sheet 03.97 Preliminary ...
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... Packages, Emulators, Evaluation Boards, HLL-Debuggers, Simulators, Logic Analyzer Disassemblers, Programming Boards Ambient Temperature Range ˚C 80-Pin MQFP Package (0.65 mm pitch) This document describes the SAB-C161V-L16M, the SAB-C161K-L16M and the SAB-C161O-L16M. For simplicity all versions are referred to by the term C161 throughout this document whenever possible. ...
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... It combines high CPU performance ( million instructions per second) with high peripheral functionality and enhanced IO-capabilities. The C161 derivatives are especially suited for cost sensitive applications. Figure 1 Logic Symbol Ordering Information Type Ordering Code SAB-C161V-L16M Q67121-C1007 SAB-C161K-L16M Q67121-C1060 SAB-C161O-L16M Q67121-C1061 Semiconductor Group 1996 Intermediate Version Package P-MQFP-80-1 P-MQFP-80-1 P-MQFP-80-1 2 ...
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Figure 2 Pin Configuration Square MQFP-80 Package (top view) Note: The marked signals are not available on all C161 derivatives. Please refer to the detailed description below. Semiconductor Group 1996 Intermediate Version 3 C161 ...
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Pin Definitions and Functions Symbol Pin Input Number Output XTAL1 2 I XTAL2 3 O P3.2 – 5 – I/O P3. I/O 12 I/O 13 ...
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Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output WR WRL ALE PORT0: I/O P0L.0 – 29 – P0L.7, 36 P0H – P0H.7 46 PORT1: I/O P1L.0 – ...
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Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output RSTOUT 66 O NMI 67 I P6.0 – I/O P6 P2.9 – I/O P2.15 78 I/O ...
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Pin Definitions and Functions (cont’d) Symbol Pin Input Number Output 38, 63 Semiconductor Group 1996 Intermediate Version Function Digital Supply Voltage during normal operation and ...
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Device Cross-Reference The table below describes the differences between the three derivatives described in this data sheet. This table provides an overview on the capabilities of each derivative for a quick comparison. Feature Internal RAM Size (IRAM) Chip Select Signals ...
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Functional Description The architecture of the C161 combines advantages of both RISC and CISC processors and of advanced peripheral subsystems in a very well-balanced way. The following block diagram gives an overview of the different on-chip components and of the ...
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... I/O ports are organized within the same linear address space which includes 4 MBytes. The entire memory space can be accessed bytewise or wordwise. Particular portions of the on-chip memory have additionally been made directly bit addressable. The C161 is prepared to incorporate on-chip mask-programmable ROM for code or constant data. ...
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Central Processing Unit (CPU) The main core of the CPU consists of a 4-stage instruction pipeline, a 16-bit arithmetic and logic unit (ALU) and dedicated SFRs. Additional hardware has been spent for a separate multiply and divide unit, a bit-mask ...
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The CPU disposes of an actual register context consisting wordwide GPRs which are physically allocated within the on-chip RAM area. A Context Pointer (CP) register determines the base address of the active register bank to be ...
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Interrupt System With an interrupt response time within a range from just 315 ns to 750 ns (in case of internal program execution), the C161 is capable of reacting very fast to the occurence of non-deterministic events. The architecture of ...
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Source of Interrupt or PEC Service Request External Interrupt 1 External Interrupt 2 External Interrupt 3 External Interrupt 4 External Interrupt 5 External Interrupt 6 External Interrupt 7 GPT1 Timer 2 GPT1 Timer 3 GPT1 Timer 4 GPT2 Timer 5 ...
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The C161 also provides an excellent mechanism to identify and to process exceptions or error conditions that arise during run-time, so-called ‘Hardware Traps’. Hardware traps cause immediate non-maskable system reaction which is similar to a standard interrupt service (branching to ...
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General Purpose Timer (GPT) Units The GPT units represent a very flexible multifunctional timer/counter structure which may be used for many different time related tasks such as event timing and counting, pulse width and duty cycle measurements, pulse generation, or ...
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In addition to their basic operating modes, timers T2 and T4 may be configured as reload or capture registers for timer T3. When used as capture or reload registers, timers T2 and T4 are stopped. The contents of timer T3 ...
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... The Watchdog Timer represents one of the fail-safe mechanisms which have been implemented to prevent the controller from malfunctioning for longer periods of time. The Watchdog Timer is always enabled after a reset of the chip, and can only be disabled in the time interval until the EINIT (end of initialization) instruction has been executed. Thus, the chip’s start-up procedure is always monitored ...
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Serial Channels Serial communication with other microcontrollers, processors, terminals or external peripheral components is provided by two serial interfaces with different functionality, an Asynchronous/ Synchronous Serial Channel (ASC0) and a High-Speed Synchronous Serial Channel (SSC). The ASC0 is upward compatible ...
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... Move (negated) direct bit to direct bit AND/OR/XOR direct bit with direct bit Compare direct bit to direct bit Bitwise modify masked high/low byte of bit-addressable direct word memory with immediate data Compare word (byte) operands Compare word data to GPR and decrement GPR by 1/2 ...
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... Software Reset Enter Idle Mode Enter Power Down Mode (supposes NMI-pin being low) Service Watchdog Timer Disable Watchdog Timer Signify End-of-Initialization on RSTOUT-pin Begin ATOMIC sequence Begin EXTended Register sequence Begin EXTended Page (and Register) sequence Begin EXTended Segment (and Register) sequence ...
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... The following table lists all SFRs which are implemented in the C161 in alphabetical order. Bit-addressable SFRs are marked with the letter “b” in column “Name”. SFRs within the Extended SFR-Space (ESFRs) are marked with the letter “E” in column “Physical Address”. ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address b F104 E 82 DP1L H b F106 E 83 DP1H H b FFC2 E1 DP2 H b FFC6 E3 DP3 H b FFCA E5 DP4 H b FFCE E7 ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address FEC4 62 PECC2 H FEC6 63 PECC3 H FEC8 64 PECC4 H FECA 65 PECC5 H FECC 66 PECC6 H FECE 67 PECC7 H b FF10 88 PSW H b ...
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Special Function Registers Overview (cont’d) Name Physical 8-Bit Address Address FE16 0B STKUN H b FF12 89 SYSCON H FE40 FF40 A0 T2CON H b FF60 B0 T2IC H FE42 FF42 A1 ...
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... Absolute Maximum Ratings Ambient temperature under bias ( SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M............................................ 0 to +70 ˚C T Storage temperature ( ) ........................................................................................ – +150 ˚ Voltage on pins with respect to ground ( CC Voltage on any pin with respect to ground ( Input current on any pin during overload condition.................................................... –10 to +10 mA Absolute sum of all input currents during overload condition ..............................................|100 mA| Power dissipation..................................................................................................................... 1.5 W Note: Stresses above those listed under “ ...
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Parameter Output low voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) Output low voltage (all other outputs) Output high voltage (PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT, RSTOUT) 1) Output high voltage (all other outputs) ...
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Notes 1) This specification is not valid for outputs which are switched to open drain mode. In this case the respective output will float and the voltage results from the external circuitry. 2) The maximum current may be drawn while ...
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Testing Waveforms AC inputs during testing are driven at 2.4 V for a logic ‘1’ and 0.4 V for a logic ‘0’. Timing measurements are made at Figure 8 Input Output Waveforms For timing purposes a port pin is no ...
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... AC Characteristics External Clock Drive XTAL1 +70 ˚C for SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M A Parameter Symbol Oscillator period TCL High time t Low time t Rise time Fall time t Figure 10 External Clock Drive XTAL1 Memory Cycle Variables The timing tables below use three variables which are derived from the BUSCONx registers and represent the special characteristics of the programmed memory cycle ...
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... AC Characteristics (cont’d) Multiplexed Bus +70 ˚C for SAB-C161V-L16M, SAB-C161K-L16M, SAB-C161O-L16M A C (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 pF L ALE cycle time = 6 TCL + 2 t Parameter ALE high time ...
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Parameter Data hold after WR ALE rising edge after RD, WR Address hold after RD, WR ALE falling edge low to Valid Data In CS hold after RD, WR ALE fall. edge to RdCS, WrCS (with RW ...
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Figure 11-1 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 1996 Intermediate Version 33 C161 ...
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Figure 11-2 External Memory Cycle: Multiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 1996 Intermediate Version 34 C161 ...
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Figure 11-3 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 1996 Intermediate Version 35 C161 ...
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Figure 11-4 External Memory Cycle: Multiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 1996 Intermediate Version 36 C161 ...
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... AC Characteristics (cont’d) Demultiplexed Bus +70 ˚C for SAB-C161K-L16M, SAB-C161O-L16M A (SAB-C161V-L16M does not provide the demultiplexed bus modes) C (for PORT0, PORT1, Port 4, ALE, RD, WR, BHE, CLKOUT) = 100 (for Port 6, CS) = 100 ALE cycle time = 4 TCL + 2 ...
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Parameter Address hold after RD, WR ALE falling edge low to Valid Data In CS hold after RD, WR ALE falling edge to RdCS, WrCS (with RW-delay) ALE falling edge to RdCS, WrCS (no RW-delay) RdCS to ...
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Figure 12-1 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Normal ALE Semiconductor Group 1996 Intermediate Version 39 C161 ...
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Figure 12-2 External Memory Cycle: Demultiplexed Bus, With Read/Write Delay, Extended ALE Semiconductor Group 1996 Intermediate Version 40 C161 ...
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Figure 12-3 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Normal ALE Semiconductor Group 1996 Intermediate Version 41 C161 ...
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Figure 12-4 External Memory Cycle: Demultiplexed Bus, No Read/Write Delay, Extended ALE Semiconductor Group 1996 Intermediate Version 42 C161 ...