ADL5391-EVALZ AD [Analog Devices], ADL5391-EVALZ Datasheet

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ADL5391-EVALZ

Manufacturer Part Number
ADL5391-EVALZ
Description
DC to 2.0 GHz Multiplier
Manufacturer
AD [Analog Devices]
Datasheet
FEATURES
Ultrafast symmetric multiplier
Unique design ensures absolute XY-symmetry
Adjustable gain scaling, α
DC-coupled throughout, 3 dB bandwidth of 2 GHz
Fully differential inputs, may be used single ended
Low noise, high linearity
Accurate, temperature stable gain scaling
Single-supply operation (4.5 V to 5.5 V @ 130 mA)
Low current power-down mode
16-lead LFCSP
APPLICATIONS
Wideband multiplication and summing
High frequency analog modulation
Adaptive antennas (diversity/phased array)
Square-law detectors and true rms detectors
Accurate polynomial function synthesis
DC capable VGA with very fast control
GENERAL DESCRIPTION
The ADL5391 draws on three decades of experience in
advanced analog multiplier products. It provides the same
general mathematical function that has been field proven to
provide an exceptional degree of versatility in function synthesis.
The most significant advance in the ADL5391 is the use of a
new multiplier core architecture, which differs markedly from
the conventional form that has been in use since 1970. The
conventional structure that employs a current mode, translinear
core is fundamentally asymmetric with respect to the X and Y
inputs, leading to relative amplitude and timing misalignments
that are problematic at high frequencies. The new multiplier
core eliminates these misalignments by offering symmetric
signal paths for both X and Y inputs. The Z input allows a signal
to be added directly to the output. This can be used to cancel a
carrier or to apply a static offset voltage.
The fully differential X, Y, and Z input interfaces are operational
over a ±2 V range, and they can be used in single-ended fashion.
The user can apply a common mode at these inputs to vary
from the internally set V
Rev. 0
Information furnished by Analog Devices is believed to be accurate and reliable. However, no
responsibility is assumed by Analog Devices for its use, nor for any infringements of patents or other
rights of third parties that may result from its use. Specifications subject to change without notice. No
license is granted by implication or otherwise under any patent or patent rights of Analog Devices.
Trademarks and registered trademarks are the property of their respective owners.
Function: V
Identical X and Y amplitude/timing responses
V
W
= α × (V
W
= α × (V
X
× V
Y
)/ 1 V + V
X
POS
× V
/2 down to ground. If these inputs
Y
)/1 V + V
Z
Z
One Technology Way, P.O. Box 9106, Norwood, MA 02062-9106, U.S.A.
Tel: 781.329.4700
Fax: 781.461.3113
are ac-coupled, their nominal voltage will be V
interfaces each present a differential 500 Ω input impedance up to
approximately 700 MHz, decreasing to 50 Ω at 2 GHz. The gain
scaling input, GADJ, can be used for fine adjustment of the gain
scaling constant (α) about unity.
The differential output can swing ±2 V about the V
common-mode and can be taken in a single-ended fashion as
well. The output common mode is designed to interface directly
to the inputs of another ADL5391. Light dc loads can be ground
referenced; however, ac-coupling of the outputs is recommended
for heavy loads.
The ENBL pin allows the ADL5391 to be disabled quickly to a
standby mode. It operates off supply voltages from 4.5 V to
5.5 V while consuming approximately 130 mA.
The ADL5391 is fabricated on Analog Devices proprietary, high
performance, 65 GHz, SOI complementary, SiGe bipolar IC
process. It is available in a 16-lead, Pb-free, LFCSP and operates
over a −40°C to +85°C temperature range. Evaluation boards
are available.
XMNS
ENBL
XPLS
VMID
FUNCTIONAL BLOCK DIAGRAM
YMNS YPLS
COMM VPOS
©2006 Analog Devices, Inc. All rights reserved.
Figure 1.
GADJ
W = αXY/1V+Z
ADL5391
DC to 2.0 GHz
Multiplier
ADL5391
POS
www.analog.com
ZMNS
ZPLS
WPLS
WMNS
/2. These input
POS
/2

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ADL5391-EVALZ Summary of contents

Page 1

... ADL5391. Light dc loads can be ground referenced; however, ac-coupling of the outputs is recommended for heavy loads. The ENBL pin allows the ADL5391 to be disabled quickly to a standby mode. It operates off supply voltages from 4 5.5 V while consuming approximately 130 mA. The ADL5391 is fabricated on Analog Devices proprietary, high performance, 65 GHz, SOI complementary, SiGe bipolar IC process ...

Page 2

... ADL5391 TABLE OF CONTENTS Features .............................................................................................. 1 Applications....................................................................................... 1 Functional Block Diagram .............................................................. 1 General Description ......................................................................... 1 Revision History ............................................................................... 2 Specifications..................................................................................... 3 Absolute Maximum Ratings............................................................ 5 ESD Caution.................................................................................. 5 Pin Configuration and Function Descriptions............................. 6 REVISION HISTORY 7/06—Revision 0: Initial Version Typical Performance Characteristics ..............................................7 General Description....................................................................... 10 Basic Theory ............................................................................... 10 Basic Connections...................................................................... 10 Evaluation Board ............................................................................ 13 Outline Dimensions ....................................................................... 15 Ordering Guide ...

Page 3

... from −2 +2.0 V, 150 Ω X stepped from − 150 Ω dBm fund = 10 MHz Fund = 200 MHz X ( dBm fund = 10 MHz Fund = 200 MHz Rev Page ADL5391 Min Typ Max Unit ...

Page 4

... ADL5391 Parameter OIP3 OIP2 Output 1 dB Compression Point Group Delay Differential Gain Error, X/Y Differential Phase Error, X/Y GAIN TRIMMING (α) Nominal Bias Input Range Gain Adjust Range REFERENCE VOLTAGE Source Current POWER AND ENABLE Supply Voltage Range Total Supply Current Disable Current ...

Page 5

... POS V section of this specification is not implied. Exposure to absolute POS 800 mW maximum rating conditions for extended periods may affect 73°C/W device reliability. 150°C −40°C to +85°C −65°C to +150°C 300°C Rev Page ADL5391 ...

Page 6

... XPLS, XMNS Differential Y-Multiplicand Inputs. 15 ENBL Chip Enable. High to enable. 16 VMID V /2 Reference Output. Connect decoupling capacitor to circuit common. POS PIN 1 12 YMNS COMM 1 INDICATOR VPOS 2 11 YPLS ADL5391 VPOS 3 10 ZPLS VPOS 4 9 ZMNS Figure 2. Pin Configuration Rev Page ...

Page 7

... FREQUENCY (MHz dBm IN FREQUENCY (MHz dBm IN 2.0 X ± INPUT = 1.0V p-p, @ 200MHz Y ± INPUT = 1.0V DC DIFFERENTIAL 1.5 1.0 0.5 0 –0.5 –1.0 –1.5 –2.0 24.5 25.5 26.5 27.5 28.5 29.5 30.5 TIME (ns) Figure 8. Large Signal Pulse Response ADL5391 200 150 100 50 –0 –50 –100 –150 –200 200 150 100 50 –0 –50 –100 –150 –200 31.5 32.5 33.5 ...

Page 8

... ADL5391 0.20 X ± INPUT = ±100mV p-p, @ 200MHz Y ± INPUT = 1.0V DC DIFFERENTIAL 0.15 0.10 0.05 0 –0.05 –0.10 –0.15 –0.20 24.5 25.5 26.5 27.5 28.5 29.5 TIME (ns) Figure 9. Small Signal Pulse Response 10MHz 30MHz 20MHz Figure 10. Harmonic Distortion at 10 MHz and 200 MHz; 0 dBm Input to X (Y) Channels –40 – TEMPERATURE (° ...

Page 9

... U –94.448 DEG 201.000 0.800 U –17.218 DEG 2001.000 0.564 U –58.167 DEG Figure 15. Input S11 1.00UFS 3001.000 1.000 Rev Page ADL5391 S22 SE S22 DIFF 3001.000 201.000 0.947 U +170.736 DEG 1001.000 0.569 U +58.257 DEG 1901.000 0.597 U –69.673 DEG 201 ...

Page 10

... Figure 4 generally not of concern unless the ADL5391 is operated down to dc (close to the point V), where expected on the output ( V). For example, when the ADL5391 is used as a VGA and a large amount of attenuation is needed, the maximum attenuation is determined by the input dc offset. ...

Page 11

... VGA mode. Figure 6 and Figure 7 show the dynamic range available in VGA mode (without optimizing the dc offsets). The speed of the ADL5391 in VGA mode allows used as an amplitude modulator. Either or both inputs can have modulation or CW applied. AM modulation is achieved by feeding CW into X (or Y) and adding AM modulation to the Y (or X) input ...

Page 12

... Figure 22 shows the configuration used. 0.7 0.6 0.5 0.4 0.3 700 800 900 1000 0.2 0.1 10dB PAD 150Ω 62Ω Figure 20. ADL5391 Used as Square Law Detector DC Output vs. Square of Input 200Ω 1.6 1.4 1.2 1.0 0.8 0.6 0.4 0.2 –0.2 Figure 21. ADL5391Used as a Square Law Detector Error vs. Power Input 56.2Ω ...

Page 13

... VPOS VPOS 0.1µ C10 100pF C12 TP TP 0.1µF COMM COMM TP14 TP12 C11 4.7µF VPOS TP13 Figure 23. ADL5391-EVALZ Evaluation Board Schematic Rev Page C15 R14 OPEN 0Ω ZP_DC C8 TP5 0.1µ TC1-1-13M T4 OPEN ZM J4 C17 ZM_DC 0.1µF ...

Page 14

... TP12, TP14 Black test loops. TP3, TP10, TP11 Yellow test loops. DUT ADL5391. Part Number TC1-1-13M+ Mini-Circuits ADL5391ACPZ Rev Page Default Value WP, ZP, YP, XP WM, ZM, YM, XM GADJ T3 and T4 are populated, but the Y and Z inputs are set up for dc operation. 0.1 μF, 0402 capacitors Open, 0402 capacitors 0 Ω ...

Page 15

... INDICATOR 12° MAX 0.90 0.85 0.80 SEATING PLANE ORDERING GUIDE Model Temperature Range ADL5391ACPZ-R2 1 −40°C to +85°C 1 ADL5391ACPZ-R7 −40°C to +85°C 1 ADL5391ACPZ-WP −40°C to +85°C 1 ADL5391-EVALZ Pb-free part. 3.00 0.60 MAX BSC SQ 0. 2.75 TOP BSC SQ VIEW 9 (BOTTOM VIEW) 0.50 8 BSC 1.50 REF 0.80 MAX 0.65 TYP ...

Page 16

... ADL5391 NOTES ©2006 Analog Devices, Inc. All rights reserved. Trademarks and registered trademarks are the property of their respective owners. D06059-0-7/06(0) T Rev Page ...

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