24LC00-/OT MICROCHIP [Microchip Technology], 24LC00-/OT Datasheet

no-image

24LC00-/OT

Manufacturer Part Number
24LC00-/OT
Description
Manufacturer
MICROCHIP [Microchip Technology]
Datasheet
Device Selection Table
Features
• Low-power CMOS technology
• Software addressability allows up to 255 devices
• 2-wire serial interface bus, I
• Automatic bus arbitration
• Wakes up to control code 0110
• General purpose output pin can be used to enable
• 100 kHz and 400 kHz compatibility
• Page write buffer for up to 16 bytes
• 10 ms max write cycle time for byte or page write
• 1,000,000 erase/write cycles
• 8-pin PDIP, SOIC or TSSOP packages
• Temperature ranges supported:
Description
The Microchip Technology Inc. 24LCS61/62 is a 1K/2K
bit Serial EEPROM developed for applications that
require many devices on the same bus but do not have
the I/O pins required to address each one individually.
These devices contain an 8 bit address register that is
set upon power-up and allows the connection of up to
255 devices on the same bus. When the process of
assigning ID values to each device is in progress, the
device will automatically handle bus arbitration if more
than one device is operating on the bus. In addition, an
external open drain output pin is available that can be
used to enable other circuitry associated with each
individual
operation with typical standby and active currents of
only 10 A and 1 mA respectively. The device has a
page write capability for up to 16 bytes of data. The
device is available in the standard 8-pin PDIP, SOIC
(150 mil), and TSSOP packages.
I
 2004 Microchip Technology Inc.
2
C is a trademark of Philips Corporation.
24LCS51
24LCS62
- 1 mA active current typical
- 10 A standby current typical at 5.5V
on the same bus
other circuitry
- Industrial (I):
Device
1K/2K Software Addressable I
system.
1K bits
2K bits
Array
Size
Low
2.5V-5.5V
2.5V-5.5V
Voltage
Range
-40°C to +85°C
current
2
C compatible
Software Write
design permits
24LCS61/24LCS62
Entire Array
Protection
Lower Half
Package Types
Block Diagram
Pin Function Table
SOIC
TSSOP
V
PDIP
V
SDA SCL
CC
SS
2
Control
EDS
Logic
C
I/O
Name
SDA
EDS
SCL
V
V
NC
CC
SS
EDS
EDS
EDS
V
Vss
Vss
NC
NC
NC
NC
Obsolete Device
NC
NC
SS
Serial EEPROM
Memory
Control
Logic
1
2
3
4
1
2
3
4
Ground
Serial Data
Serial Clock
+2.5V to 5.5V Power Supply
No Internal Connection
External Device Select Output
1
2
3
4
XDEC
Function
8
7
6
5
8
7
6
5
8
7
6
5
Sense Amp.
R/W Control
HV Generator
DS21226E-page 1
Serial Number
ID Register
Vcc
NC
SCL
SDA
V
NC
SCL
SDA
EEPROM
CC
YDEC
Vcc
NC
SCL
SDA
Array

Related parts for 24LC00-/OT

24LC00-/OT Summary of contents

Page 1

... SDA Vcc SCL 4 5 SDA SS HV Generator Memory EEPROM Control Array Logic XDEC ID Register Serial Number YDEC Sense Amp. R/W Control Function Ground Serial Data Serial Clock +2.5V to 5.5V Power Supply No Internal Connection External Device Select Output DS21226E-page 1 ...

Page 2

ELECTRICAL CHARACTERISTICS (†) Absolute Maximum Ratings V .............................................................................................................................................................................7.0V CC All inputs and outputs w.r.t. V ......................................................................................................... -0. Storage temperature ...............................................................................................................................-65°C to +150°C Ambient temperature with power applied ................................................................................................-65°C to +125°C ESD protection on all pins ...

Page 3

TABLE 1-2: AC CHARACTERISTICS All parameters apply across the specified operating ranges unless otherwise noted. Parameter Symbol Clock frequency F CLK Clock high time T HIGH Clock low time T LOW SDA and SCL rise time T R SDA and ...

Page 4

PIN DESCRIPTIONS 2.1 SDA (Serial Data) This is a bidirectional pin used to transfer addresses and data into and data out of the device open drain terminal, therefore the SDA bus requires a pull-up resistor ...

Page 5

Acknowledge Each receiving device, when addressed, is required to generate an acknowledge after the reception of each byte. The master device must generate an extra clock pulse which is associated with this Acknowledge bit. Note: The 24LCS61/62 does not ...

Page 6

FUNCTIONAL DESCRIPTION The 24LCS61/62 supports a bidirectional 2-wire bus and data transmission protocol compatible with the I protocol. The device is configured to reside common I C bus with up to 255 total 24LCS61/62 devices ...

Page 7

ASSIGNING THE ID BYTE The 24LCS61/62 device contains a special register which holds an 8-bit ID byte that is used as an address to communicate with a specific device on the bus. All Read and Write commands to the ...

Page 8

Clear Address Command The Clear Address command will clear the device ID byte from all devices on the bus and will enable all devices to respond to the Assign Address command. The master must end the command by ...

Page 9

TABLE 5-1: COMMAND SUMMARY TABLE Result if Device Has Not Yet Command Been Assigned an ID Byte Assign Address If device wins arbitration, then ID command byte will become xxh. If device loses arbitration, then ID byte will revert back ...

Page 10

... Stop condition, the master transmits additional data bytes to the 24LCS61/62, which are temporarily stored in the on-chip page buffer and will be written into the memory after the master has transmit- ted a Stop condition. If the master should transmit more than 16 bytes prior to generating the Stop condition, the address counter will roll over and the previously received data will be overwritten ...

Page 11

FIGURE 6-2: PAGE WRITE S T BUS ACTIVITY CONTROL A MASTER BYTE R T SDA LINE BUS ACTIVITY FIGURE 6-3: SET WRITE PROTECTION COMMAND ...

Page 12

ACKNOWLEDGE POLLING Since the device will not acknowledge during a write cycle, this can be used to determine when the cycle is complete (this feature can be used to maximize bus throughput). Once the Stop condition for a ...

Page 13

... To provide sequential reads the 24LCS61/62 contains an internal address pointer which is incremented by one at the completion of each operation. This address pointer allows the entire memory contents to be serially read during one operation. The internal address pointer will automatically roll over from address 7Fh (24LCS51) or FFh (24LCS62) to address 00h ...

Page 14

FIGURE 8-2: RANDOM READ S DEVICE CONTROL BYTE BYTE FIGURE 8-3: SEQUENTIAL READ BUS ACTIVITY ID MASTER BYTE SDA LINE A ...

Page 15

EXTERNAL DEVICE SELECT (EDS) PIN AND OUTPUT ENABLE (OE) BIT The External Device Select (EDS) pin is an open drain, low active output and may be used by the system designer for functions such as enabling other circuitry when ...

Page 16

APPENDIX A: REVISION HISTORY Revision D Corrections to Section 1.0, Electrical Characteristics. Revision E Add “Obsolete Device” to document header. DS21226E-page 16  2004 Microchip Technology Inc. ...

Page 17

ON-LINE SUPPORT Microchip provides on-line support on the Microchip World Wide Web site. The web site is used by Microchip as a means to make files and information easily available to customers. To view the site, the user must have ...

Page 18

READER RESPONSE It is our intention to provide you with the best documentation possible to ensure successful use of your Microchip prod- uct. If you wish to provide your comments on organization, clarity, subject matter, and ways in which ...

Page 19

... To order or obtain information, e.g., on pricing or delivery, refer to the factory or the listed sales office PART NO. X /XX Device Temperature Package Range 2 Device 24AA00 128 bit 1.8V I 24AA00T128 bit 1. 24LC00 128 bit 2.5V I 24LC00T 128 bit 2. 24C00 128 bit 5.0V I 24C00T 128 bit 5. Temperature Range Blank = + - + ...

Page 20

NOTES: DS21226E-page 20  2004 Microchip Technology Inc. ...

Page 21

... October 2003. The Company’s quality system processes and procedures are for its PICmicro 8-bit MCUs, K ® EE devices, Serial EEPROMs, microperipherals, nonvolatile memory and analog products. In addition, Microchip’s quality system for the design and manufacture of development systems is ISO 9001:2000 certified. DS21226E-page 21 L code hopping ® ...

Page 22

W ORLDWIDE AMERICAS Corporate Office 2355 West Chandler Blvd. Chandler, AZ 85224-6199 Tel: 480-792-7200 Fax: 480-792-7277 Technical Support: 480-792-7627 Web Address: www.microchip.com Atlanta 3780 Mansell Road, Suite 130 Alpharetta, GA 30022 Tel: 770-640-0034 Fax: 770-640-0307 Boston 2 Lan Drive, Suite ...

Related keywords