M58LW032 STMICROELECTRONICS [STMicroelectronics], M58LW032 Datasheet - Page 12

• Manufacturer Part Number: M58LW032
• Description: 32 Mbit 2Mb x16, Uniform Block, Burst 3V Supply Flash Memory
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

M58LW032A
one cycle before. Valid Data Ready Low, V
dicates that the data is not, or will not be valid. Val-
id Data Ready in a high-impedance state indicates
that valid data is or will be available.
Unless Synchronous Burst Read has been select-
ed, Valid Data Ready is high-impedance. It may be
tied to other components with the same Valid Data
Ready signal to create a unique System Ready
signal.
The Valid Data Ready, R, output has an internal
pull-up resistor of approximately 1 M
from V
up resistor of the correct value to meet the external
timing requirements for Valid Data Ready rising.
Refer to Figure 19.
Ready/Busy (RB). The Ready/Busy output, RB,
is an open-drain output that can be used to identify
if the Program/Erase Controller is currently active.
When Ready/Busy is high impedance, the memo-
ry is ready for any Read, Program or Erase opera-
tion. Ready/Busy is Low, V
Erase operations. When the device is busy it will
not accept any additional Program or Erase com-
mands except Program/Erase Suspend. When the
Program/Erase Controller is idle, or suspended,
Ready Busy can float High through a pull-up resis-
tor.
The use of an open-drain output allows the Ready/
Busy pins from several memories to be connected
to a single pull-up resistor. A Low will then indicate
that one, or more, of the memories is busy.
Ready/Busy is not Low during a reset unless the
reset was applied when the Program/Erase Con-
12/61
DDQ
, designers should use an external pull-
OL
, during Program and
powered
OL
, in-
troller was active; Ready/Busy can rise before Re-
set/Power-Down rises.
Program/Erase Enable (V
Erase Enable input, V
blocks, preventing Program and Erase operations
from affecting their data.
Program/Erase Enable must be kept High during
all Program/Erase Controller operations, other-
wise the operations is not guaranteed to succeed
and data may become corrupt.
V
supply to the internal core of the memory device.
It is the main power supply for all operations
(Read, Program and Erase).
V
supply to the I/O pins and enables all Outputs to
be powered independently from V
tied to V
It is recommended to power-up and power-down
V
would result in data corruption.
V
the core power supply. It must be connected to the
system ground.
V
the input/output circuitry driven by V
must be connected to V
Note: Each device in a system should have
V
capacitor close to the pin (high frequency, in-
herently low inductance capacitors should be
as close as possible to the package). See Fig-
ure 10, AC Measurement Load Circuit.
DD
DDQ
DD
SS
SSQ
DD
and V
Ground. Ground, V
Supply Voltage. V
and V
Ground. V
Supply Voltage. V
DD
DDQ
DDQ
or can use a separate supply.
together to avoid any condition that
decoupled with a 0.1µF ceramic
SSQ
ground is the reference for
PP,
SS
DD
SS,
DDQ
.
PP
is used to protect all
provides the power
is the reference for
). The
provides the power
DD
. V
DDQ
DDQ
Program/
. V
can be
SSQ