HYB25D256160CC-5 QIMONDA [Qimonda AG], HYB25D256160CC-5 Datasheet - Page 19

• Manufacturer Part Number: HYB25D256160CC-5
• Description: 256-Mbit Double-Data-Rate SDRAM
• Manufacturer: QIMONDA [Qimonda AG]

1) This table applies when CKE n-1 was HIGH and CKE n is HIGH (see
2) This table is bank-specific, except where noted, i.e., the current state is for a specific bank and the commands shown are those allowed
3) Current state definitions: Idle: The bank has been precharged, and
4) The following states must not be interrupted by a command issued to the same bank. Precharging: Starts with registration of a Precharge
5) The following states must not be interrupted by any executable command; Deselect or NOP commands must be applied on each positive
6) All states and sequences not shown are illegal or reserved.
7) Not bank-specific; requires that all banks are idle.
8) Reads or Writes listed in the Command/Action column include Reads or Writes with Auto Precharge enabled and Reads or Writes with
9) May or may not be bank-specific; if all/any banks are to be precharged, all/any must be in a valid state for precharging.
10) Not bank-specific; BURST TERMINATE affects the most recent Read burst, regardless of bank.
11) Requires appropriate DM masking.
Rev. 2.3, 2007-03
03062006-8CCM-VPUW
Current State
Any
Idle
Row Active
Read (Auto
Precharge
Disabled)
Write (Auto
Precharge
Disabled)
was self refresh).
to be issued to that bank when in that state. Exceptions are covered in the notes below.
and
Auto Precharge disabled, and has not yet terminated or been terminated. Write: A Write burst has been initiated, with Auto Precharge
disabled, and has not yet terminated or been terminated.
command and ends when
command and ends when
registration of a Read command with Auto Precharge enabled and ends when
state. Write w/Auto Precharge Enabled: Starts with registration of a Write command with Auto Precharge enabled and ends when
been met. Once
issued on any clock edge occurring during these states. Allowable commands to the other bank are determined by its current state and
according to
clock edge during these states. Refreshing: Starts with registration of an Auto Refresh command and ends when
met, the DDR SDRAM is in the “all banks idle” state. Accessing Mode Register: Starts with registration of a Mode Register Set command
and ends when
registration of a Precharge All command and ends when
Auto Precharge disabled.
t
RCD
has been met. No data bursts/accesses and no register accesses are in progress. Read: A Read burst has been initiated, with
Table
CS
H
L
L
L
L
L
L
L
L
L
L
L
L
L
t
t
MRD
RP
14.
is met, the bank is in the idle state. Deselect or NOP commands, or allowable commands to the other bank should be
has been met. Once
RAS CAS WE
X
H
L
L
L
H
H
L
H
L
H
H
H
L
t
t
RCD
RP
is met. Once
is met. Once
X
H
H
L
L
L
L
H
L
H
H
L
L
H
X
H
H
H
L
H
L
L
H
L
L
H
L
L
Truth Table 3: Current State Bank n - Command to Bank n (same bank)
t
MRD
t
RP
t
RCD
is met, the DDR SDRAM is in the “all banks idle” state. Precharging All: Starts with
is met, the bank is in the idle state. Row Activating: Starts with registration of an Active
Command
Deselect
No Operation
Active
AUTO REFRESH
MODE REGISTER
SET
Read
Write
Precharge
Read
Precharge
BURST
TERMINATE
Read
Write
Precharge
is met, the bank is in the “row active” state. Read w/Auto Precharge Enabled: Starts with
t
RP
is met. Once
19
t
RP
Table 12
has been met. Row Active: A row in the bank has been activated,
Action
NOP. Continue previous operation.
NOP. Continue previous operation.
Select and activate row
—
—
Select column and start Read burst
Select column and start Write burst
Deactivate row in bank(s)
Select column and start new Read burst
Truncate Read burst, start Precharge
BURST TERMINATE
Select column and start Read burst
Select column and start Write burst
Truncate Write burst, start Precharge
t
RP
is met, all banks is in the idle state.
t
and after
RP
has been met. Once
HY[B/I]25D256[16/40/80]0C[E/C/F/T](L)
t
XSNR
256 Mbit Double-Data-Rate SDRAM
/
t
XSRD
has been met (if the previous state
t
RP
is met, the bank is in the idle
Internet Data Sheet
t
RFC
is met. Once
TABLE 13
Note
1)2)3)4)5)6)
1) to 6)
1) to 6)
1) to7)
1) to 7)
1) to 6),8)
1) to 6),8)
1) to 6),9)
1) to 6),8)
1) to 6),9)
1) to 6),10)
1) to 6), 8),11)
1) to 6),8)
1) to 6),9),11)
t
RP
t
RFC
has
is