HYB18L256169BF QIMONDA [Qimonda AG], HYB18L256169BF Datasheet - Page 32

• Manufacturer Part Number: HYB18L256169BF
• Description: 256-Mbit Mobile-RAM
• Manufacturer: QIMONDA [Qimonda AG]

2.4.8.2
A READ or WRITE burst with Auto Precharge enabled can be interrupted by a subsequent READ or WRITE
command issued to a different bank.
Figure 37
to bank m. The READ to bank m will interrupt the READ to bank n, CAS latency later. The precharge to bank n
will begin when the READ to bank m is registered.
Figure 38
to bank m. The precharge to bank n will begin when the WRITE to bank m is registered. DQM should be pulled
HIGH two clock cycles prior to the WRITE to prevent bus contention.
Figure 39
to bank m. The precharge to bank n will begin
data-in to bank n is one clock cycle prior to the READ to bank m.
Figure 40
Precharge) to bank m. The precharge to bank n will begin
valid data-in to bank n is one clock cycle prior to the WRITE to bank m.
Figure 37
Figure 38
Data Sheet
shows a READ with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto Precharge)
shows a WRITE with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
shows a READ with Auto Precharge to bank n, interrupted by a READ (with or without Auto Precharge)
shows a WRITE with Auto Precharge to bank n, interrupted by a WRITE (with or without Auto
CONCURRENT AUTO PRECHARGE
READ with Auto Precharge Interrupted by READ
READ with Auto Precharge Interrupted by WRITE
t
WR
after the new command to bank m is registered. The last valid
32
t
WR
after the WRITE to bank m is registered. The last
HY[B/E]18L256169BF-7.5
256-Mbit Mobile-RAM
Functional Description
02032006-MP0M-7FQG
Rev. 1.02, 2006-12