SC410 SEMTECH [Semtech Corporation], SC410 Datasheet - Page 19

• Manufacturer Part Number: SC410
• Description: 3A EcoSpeed TM Step-Down Regulator with LDO and Ultrasonic Power Save
• Manufacturer: SEMTECH [Semtech Corporation]

Applications Information (continued)
Stability Considerations
Unstable operation is possible with adaptive on-time con-
trollers, and usually takes the form of double-pulsing or
ESR loop instability.
Double-pulsing occurs due to switching noise seen at the
FB input or because the FB ripple voltage is too low. This
causes the FB comparator to trigger prematurely after the
minimum off -time has expired. In extreme cases the noise
can cause three or more successive on-times. Double-
pulsing will result in higher ripple voltage at the output,
but in most applications it will not aff ect operation. This
form of instability can usually be avoided by providing the
FB pin with a smooth, clean ripple signal that is at least
10mVp-p, which may dictate the need to increase the ESR
of the output capacitors. It is also imperative to provide a
proper PCB layout.
An alternate method to eliminate doubling-pulsing is to
add a small (~ 10pF) capacitor across the upper feedback
resistor, as shown in Figure 9. This capacitor should be left
unpopulated unless it can be confirmed that double-
pulsing exists. Adding the C
ripple into FB to help eliminate the problem. An optional
connection on the PCB should be provided for this
capacitor.
ESR loop instability is caused by insufficient ESR. The
details of this stability issue are discussed in the ESR
Requirements section. The best method for checking sta-
bility is to apply a zero-to-full load transient and observe
the output voltage ripple envelope for overshoot and
ringing. Ringing for more than one cycle after the initial
step is an indication that the ESR should be increased.
Figure 9 — Capacitor Coupling to FB Pin
V
OUT
C
R1
TOP
TOP
R2
capacitor will couple more
To FB pin
One simple method of solving this problem is to add trace
resistance in the high current output path. A side eff ect of
adding trace resistance is a decrease in load regulation.
ESR Requirements
A minimum ESR is required for two reasons. The first
reason is to generate enough output ripple voltage to
provide 10mVp-p at the FB pin (after the resistor divider)
to avoid double-pulsing.
The second reason is to prevent instability due to insuffi -
cient ESR. The on-time control regulates the valley of the
output ripple voltage. This ripple voltage is the sum of the
two voltages. One is the ripple generated by the ESR, the
other is the ripple due to capacitive charging and dis-
charging during the switching cycle. For most applica-
tions, the total output ripple voltage is dominated by the
output capacitors, typically SP or POSCAP devices. For
stability the ESR zero of the output capacitor should be
lower than approximately one-third the switching fre-
quency. The formula for minimum ESR is shown by the
following equation.
Using Ceramic Output Capacitors
When applications use ceramic output capacitors, the ESR
is normally too small to meet the previously stated ESR
criteria. In these applications it is necessary to add a small
signal injection network as shown in Figure 10. In this
network R
generate an in-phase ripple voltage comparable to the
ripple seen on higher ESR capacitors. C
capacitor used to AC couple the generated ripple onto the
FB pin.
E
SR
L
MIN
and C
2
L
filter the LX switching waveform to
C
3
OUT
f
sw
C
is a coupling
SC410
19