CS5212GD14 ONSEMI [ON Semiconductor], CS5212GD14 Datasheet - Page 7

• Manufacturer Part Number: CS5212GD14
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ONSEMI [ON Semiconductor]

beginning of the next oscillator cycle will set the latch so that
the main switch can be turned on and the regulator output
voltage ramps up. When the output voltage achieves a level
set by the COMP voltage, the main switch will be turned off.
The V
as required to ensure the regulator output voltage tracks the
COMP voltage. Since the COMP voltage increases
gradually, the soft−start can be achieved. The start−up
period ends when the output voltage reaches the level set by
the external resistor divider.
Output Enable
exceeds the 0.5 V offset built into the PWM comparator, the
COMP pin can also be used for an enable function. Hold the
COMP pin below 0.4 V with an open collector circuit to
disable the output. When the COMP pin is released to enable
startup, the user must ensure there is no leakage current from
the enable circuit into COMP. During normal operation the
COMP output is driven with only 5.0 mA to 30 mA internally.
Hiccup Mode Overcurrent Protection
and IS− pins is less than the 60 mV overcurrent threshold. If
the threshold is exceeded, the overcurrent fault latch is set,
the high side gate driver is forced low, and the COMP pin is
discharged with 5.0 mA. There is no switching until the
COMP voltage drops below a 0.25 V threshold. Then, the
fault latch is cleared and a soft−start is initiated. The low
effective duty cycle during hiccup overcurrent greatly
reduces component stress for an extended fault.
Inductor Current Sensing
current, CS5212 provides the users with the possibility of
using loss−less inductor sensing technique. This sensing
technique utilizes the Equivalent Series Resistance (ESR) of
the inductor to sense the current. The output current is
sensed through an RC network in parallel with the inductor
as shown in Figure 4. The voltage across the small capacitor
is then fed to the OC comparator.
Since there can be no switching until the COMP pin
Under normal load conditions, the voltage across the IS+
Besides using a current sense resistor to sense inductor
2
V
control loop will adjust the main switch duty cycle
IN
Q2
Q1
Figure 4. Inductor Current Sensing
R
L
IS+
RL
C
IS−
C
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to that of the inductor, the voltage across the capacitor is
proportional to the inductor current by a factor of the
inductor ESR. In practice, the user should ensure that under
all component tolerances, the RC time constant is larger than
the L/R time constant. This will keep the high frequency
gain for V
avoid unnecessary OCP tripping during short duration
overcurrent situations.
inductor ESR current sensing technique is lossless, but is not
as accurate due to variation in the ESR from inductor to
inductor and over temperature. For typical inductor ESR, the
0.39%/°C positive temperature coefficient will reduce the
current limit at high temperature, and will help prevent
thermal runaway, but will force an increased design target at
room temperature. This technique can be more accurate than
using a PCB trace, since PCB copper thickness can vary
10−20%, compared to 1% variation in wire diameter
thickness typical of inductors.
Remote Voltage Sensing
the load is located far away from the regulator. The SGND
pin is dedicated to the differential remote sensing. The
negative remote sense line is connected to SGND pin
directly, while the positive remote sense line is usually
connected to the top of the feedback voltage divider. To
prevent over−voltage condition caused by open remote
sense lines, the divider should also be locally connected to
the output of the regulator through a low value resistor. That
resistor is used to compensate for the voltage drop across the
output power cables.
If the values of R and C are chosen such that:
Then the voltage across the capacitor C will be:
Therefore, if the time constant of the RC network is equal
Compared with conventional resistor sensing, the
The CS5212 has the capability to sense the voltage when
C
(s)/I
L
(s) less than the low frequency gain, and
V C + R L I L
R L
L
+ RC