CS5212GD14 ONSEMI [ON Semiconductor], CS5212GD14 Datasheet - Page 9

• Manufacturer Part Number: CS5212GD14
• Description: Low Voltage Synchronous Buck Controller
• Manufacturer: ONSEMI [ON Semiconductor]

the design must first predict the MOSFET power dissipation.
Once the dissipation is known, the heat sink thermal
impedance can be calculated to prevent the specified
maximum case or junction temperatures from being exceeded
at the highest ambient temperature. Power dissipation has two
primary contributors: conduction losses and switching losses.
The control or upper MOSFET will display both switching
and conduction losses. The synchronous or lower MOSFET
will exhibit only conduction losses because it switches into
nearly zero voltage. However, the body diode in the
synchronous MOSFET will suffer diode losses during the
non−overlap time of the gate drivers.
can be approximated from:
the MOSFET is ON while the second term represents the
switching losses. The third term is the losses associated with
the control and synchronous MOSFET output charge when
the control MOSFET turns ON. The output losses are caused
by both the control and synchronous MOSFET but are
dissipated only in the control FET. The fourth term is the loss
due to the reverse recovery time of the body diode in the
synchronous MOSFET. The first two terms are usually
adequate to predict the majority of the losses.
current in the control MOSFET:
I RMS,CNTL + D @ [(I Lo,MAX 2 ) I Lo,MAX @ I Lo,MIN
inductor of value Lo:
applied gate drive voltage.
gate−to−source charge plus the gate−to−drain charge. This
may be specified in the data sheet or approximated from the
gate−charge curve as shown in the Figure 5.
P D,CONTROL + (I RMS,CNTL 2 @ R DS(on) )
For the upper or control MOSFET, the power dissipation
The first term represents the conduction or IR losses when
Where I
I
I
I
D is the duty cycle of the converter:
DI
R
Q
Lo,MAX
Lo,MIN
O,MAX
DS(on)
switch
Lo
) (I Lo,MAX @ Q switch I g @ V IN @ f SW )
) (Q oss 2 @ V IN @ f SW ) ) (V IN @ Q RR @ f SW )
is the peak−to−peak ripple current in the output
DI Lo + (V IN * V OUT ) @ D (Lo @ f SW )
is the minimum output inductor current:
is the maximum converter output current.
RMS,CNTL
is the ON resistance of the MOSFET at the
is the maximum output inductor current:
is the post gate threshold portion of the
I Lo,MAX + I O,MAX 2 ) DI Lo 2
I Lo,MIN + I O,MAX 2 * DI Lo 2
Q switch + Q gs2 ) Q gd
) I Lo,MIN 2 ) 3] 1 2
D + V OUT V IN
is the RMS value of the trapezoidal
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9
dissipation can be approximated from:
the MOSFET is ON and the second term represents the diode
losses that occur during the gate non−overlap time.
control MOSFET with the exception of:
I RMS,SYNCH + 1 * D
where:
designer can calculate the required thermal impedance to
maintain a specified junction temperature at the worst case
ambient operating temperature
where;
P D,SYNCH + (I RMS,SYNCH 2 @ R DS(on) )
V
I
V
f
Q
V
Q
Q
For the lower or synchronous MOSFET, the power
The first term represents the conduction or IR losses when
All terms were defined in the previous discussion for the
Vf
t_nonoverlap is the non−overlap time between the upper
When the MOSFET power dissipations are known, the
q
q
g
sw
GS_TH
@ [(I Lo,MAX 2 ) I Lo,MAX @ I Lo,MIN ) I Lo,MIN 2 ) 3] 1 2
T
JC
IN
G
g
RR
oss
Commonly specified in the data sheet.
sheet.
diode at the converter output current.
and lower gate drivers to prevent cross conduction. This
time is usually specified in the data sheet for the control
IC.
MOSFET.
is the output current from the gate driver IC.
diode
Q
Figure 5. MOSFET Switching Characteristics
is the total thermal impedance (q
is the gate drive voltage.
is the switching frequency of the converter.
is the MOSFET total gate charge to obtain R
) (Vf diode @ I O,MAX 2 @ t_nonoverlap @ f SW )
GS1
is the junction−to−case thermal impedance of the
is the input voltage to the converter.
is the reverse recovery charge of the lower MOSFET.
is the MOSFET output charge specified in the data
is the forward voltage of the MOSFET’s intrinsic
Q
GS2
q T t (T J * T A ) P D
Q
GD
I
D
JC
+ q
V
DRAIN
SA
V
GATE
).
DS(on)
.