MCF5329DS ANALOGICTECH [Advanced Analogic Technologies], MCF5329DS Datasheet
MCF5329DS
Related parts for MCF5329DS
MCF5329DS Summary of contents
Page 1
... Freescale Semiconductor, Inc., 2006. All rights reserved. • Preliminary Rev. 0.1, 03/2006 ® Table of Contents 1 MCF532x Family Configurations .........................2 2 Ordering Information ...........................................3 3 Signal Descriptions..............................................3 4 Mechanicals and Pinouts ..................................10 5 Preliminary Electrical Characteristics ................15 6 Revision History ................................................46 MCF5329DS ...
Page 2
MCF532x Family Configurations 1 MCF532x Family Configurations The following table compares the various device derivatives available within the MCF532x family. ColdFire Version 3 Core with EMAC (Enhanced Multiply-Accumulate Unit) Core (System) Clock Peripheral and External Bus Clock (Core clock ÷ ...
Page 3
Ordering Information Freescale Part Number MCF5327CVM240 MCF5327 RISC Microprocessor, 196 MAPBGA MCF5328CVM240 MCF5328 RISC Microprocessor, 256 MAPBGA MCF5329CVM240 MCF5329 RISC Microprocessor, 256 MAPBGA 3 Signal Descriptions The following table lists all the MCF532x pins grouped by function. The “Dir” ...
Page 4
Signal Descriptions Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO FB_CLK — 2 RCON — DRAMSEL — A[23:22] — A[21:16] — A[15:14] — A[13:11] — A10 — A[9:0] — D[31:16] — D[15:1] — — BE/BWE[3:0] ...
Page 5
Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO FB_CS0 — SD_A10 — SD_CKE — SD_CLK — SD_CLK — SD_CS1 — SD_CS0 — SD_DQS3 — SD_DQS2 — SD_SCAS — SD_SRAS — SD_SDR_DQS — SD_WE — IRQ7 ...
Page 6
Signal Descriptions Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO FEC_RXD0 PFECH1 FEC_CRS PFECH0 FEC_TXD[3:1] PFECL[7:5] FEC_TXER PFECL4 FEC_RXD[3:1] PFECL[3:1] FEC_RXER PFECL0 LCD_D17 PLCDDH1 LCD_D16 PLCDDH0 LCD_D17 PLCDDH1 LCD_D16 PLCDDH0 LCD_D15 PLCDDM7 LCD_D14 PLCDDM6 LCD_D13 PLCDDM5 LCD_D12 ...
Page 7
Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO USBOTG_M — USBOTG_P — USBHOST_M — USBHOST_P — CANRX and CANTX do not have dedicated bond pads. Please refer to the following pins for muxing: I2C_SDA, SSI_RXD, or LCD_D16 ...
Page 8
Signal Descriptions Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO QSPI_CS0 PQSPI3 QSPI_CLK PQSPI2 QSPI_DIN PQSPI1 QSPI_DOUT PQSPI0 U1CTS PUARTL7 U1RTS PUARTL6 U1TXD PUARTL5 U1RXD PUARTL4 U0CTS PUARTL3 U0RTS PUARTL2 U0TXD PUARTL1 U0RXD PUARTL0 Note: The UART2 ...
Page 9
Table 3. MCF5327/8/9 Signal Information and Muxing (continued) Signal Name GPIO 6 TEST — 7 PLL_TEST — EVDD — IVDD — PLL_VDD — SD_VDD — USBOTG_VDD — VSS — PLL_VSS — USBHOST_VSS — NOTES: 1 Refers to pin’s primary function. ...
Page 10
Mechanicals and Pinouts 4 Mechanicals and Pinouts This section contains drawings showing the pinout and the packaging and mechanical characteristics of the MCF532x devices. The mechanical drawings are the latest revisions at the time of publication of this document. The ...
Page 11
Pinout—256 MAPBGA Figure 1 shows a pinout of the MCF5328CVM240 and MCF5329CVM240 devices. The pin at location N13 (PLL_TEST) must be left floating, else improper operation of the PLL module will occur FEC_ LCD_ LCD_ ...
Page 12
Mechanicals and Pinouts 4.2 Package Dimensions—256 MAPBGA Figure 2 shows MCF5328CVM240 and MCF5329CVM240 package dimensions Laser mark for pin A1 identification in this area E Top View 0.20 15X ...
Page 13
Pinout—196 MAPBGA The pinout for the MCF5327CVM240 package is shown below LCD_ LCD_ LCD_ A DT1IN LCD_ LCD_ LCD_ B D2TIN LCD_ LCD_ C DT3IN DT0IN D2 D7 LCD_ ...
Page 14
Mechanicals and Pinouts 4.4 Package Dimensions—196 MAPBGA Figure 4 shows the MCF5327CVM240 package dimensions Laser mark for pin 1 Y identification in this area E Top View 0. 13X 3 ...
Page 15
Preliminary Electrical Characteristics This document contains electrical specification tables and reference timing diagrams for the MCF5329 microcontroller unit. This section contains detailed information on power considerations, DC/AC electrical characteristics, and AC timing specifications of MCF5329. The electrical specifications are ...
Page 16
Preliminary Electrical Characteristics 5 Power supply must maintain regulation within operating EV and operating maximum current conditions. If positive injection current (V than I , the injection current may flow out going out of regulation. Insure external ...
Page 17
For most applications P < P I/O INT P is neglected) is: I/O Solving equations 1 and 2 for K gives: where constant pertaining to the particular part. K can be determined from P (at equilibrium) for ...
Page 18
Preliminary Electrical Characteristics Table 7. DC Electrical Specifications (continued) Characteristic Input Leakage Current Input-only pins CMOS Output High Voltage I = –5 CMOS Output Low Voltage I = 5.0 ...
Page 19
Board EV / addition to the above filter circuitry, a 0.01 F capacitor is also recommended in parallel with those shown. 5.4.3 Supply Voltage Sequencing and Separation Cautions Figure 7 shows situations in sequencing the I/O V (PLLV ...
Page 20
Preliminary Electrical Characteristics 5.4.3.1 Power Up Sequence If EV /SDV are powered up with pad output drivers connected to the EV how long after EV /SDV powers up before SDV or PLLV by more ...
Page 21
Estimated Power Consumption vs. Core Frequency 300 250 200 150 100 Figure 8. Estimated Maximum RUN Mode Power Consumption Table 8 lists estimated maximum power and current consumption for the device in various operating modes. Table 8. ...
Page 22
Preliminary Electrical Characteristics 5.6 Oscillator and PLL Electrical Characteristics Num Characteristic 1 PLL Reference Frequency Range Crystal reference External reference 2 Core frequency 1 CLKOUT Frequency Crystal Start-up Time 4 EXTAL Input High Voltage 4 Crystal Mode ...
Page 23
The timings are also valid for inputs sampled on the negative clock edge. FB_CLK (80MHz) Input Setup And Hold Input Rise Time Input Fall Time FB_CLK B4 Inputs Figure 9. General Input Timing Requirements 5.7.1 FlexBus A multi-function external ...
Page 24
Preliminary Electrical Characteristics Num Characteristic Frequency of Operation FB1 Clock Period (FB_CLK) FB2 Address, Data, and Control Output Valid (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0] and OE) FB3 Address, Data, and Control Output Hold (A[23:0], D[31:0], FB_CS[5:0], R/W, TS, BE/BWE[3:0], ...
Page 25
FB_CLK A[23:0] D[31:0] R/W TS FB_CSn BE/BWEn OE TA 5.8 SDRAM Bus The SDRAM controller supports accesses to main SDRAM memory from any internal master. It supports either standard SDRAM or double data rate (DDR) SDRAM, but it does not ...
Page 26
Preliminary Electrical Characteristics Table 11. SDR Timing Specifications (continued) Symbol Characteristic SD4 Pulse Width Low SD5 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Valid SD6 Address, SD_CKE, SD_CAS, SD_RAS, SD_WE, SD_BA, SD_CS[1:0] - Output Hold SD7 SD_SDR_DQS Output ...
Page 27
SD2 SD1 SD_CLK0 SD2 SD_CLK1 SD_CSn CMD SD_RAS SD_CAS SD_WE SD5 A[23:0] ROW SD_BA[1:0] SDDM D[31:0] SD2 SD_CLK0 SD2 SD_CLK1 SD_CSn, SD_RAS, CMD SD_CAS, SD_WE SD5 A[23:0], ROW SD_BA[1:0] SDDM SD_DQS (Measured at Output Pin) SD_DDQS (Measured at Input Pin) ...
Page 28
Preliminary Electrical Characteristics 5.8.2 DDR SDRAM AC Timing Characteristics When using the SDRAM controller in DDR mode, the following timing numbers must be followed to properly latch or drive data onto the memory bus. All timing numbers are relative to ...
Page 29
Data input skew is derived from each DQS clock edge. It begins with a DQS transition and ends when the last data line becomes valid. This input skew must include DDR memory output skew and system level board skew ...
Page 30
Preliminary Electrical Characteristics SD_CLK SD_CLK SD_CSn,SD_WE, SD_RAS, SD_CAS A[13:0] SD_DQS3/SD_DQS2 D[31:24]/D[23:16] SD_DQS3/SD_DQS2 D[31:24]/D[23:16] 5.9 General Purpose I/O Timing Num G1 FB_CLK High to GPIO Output Valid G2 FB_CLK High to GPIO Output Invalid G3 GPIO Input Valid to FB_CLK High ...
Page 31
FB_CLK GPIO Outputs GPIO Inputs 5.10 Reset and Configuration Override Timing Table 14. Reset and Configuration Override Timing Num R1 RESET Input valid to FB_CLK High R2 FB_CLK High to RESET Input invalid 1 R3 RESET Input valid Time R4 ...
Page 32
Preliminary Electrical Characteristics Refer to the CCM chapter of the MCF5329 Reference Manual for more information. 5.11 LCD Controller Timing Specifications This sections lists the timing specifications for the LCD Controller. Num T1 LCD_LSCLK Period T2 Pixel data setup time ...
Page 33
T1 LCD_VSYNC T2 LCD_HSYNC LCD_OE LCD_LD[17:0] Line Y T5 LCD_HSYNC LCD_LSCLK LCD_OE LCD_LD[15:0] Figure 20. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Table 16. 4/8/12/16/18 Bit/Pixel TFT Color Mode Panel Timing Number Description T1 End of LCD_OE to beginning of ...
Page 34
Preliminary Electrical Characteristics LCD_LSCLK LCD_LD D320 LCD_SPL_SPR T2 LCD_HSYNC T4 LCD_CLS LCD_PS T7 LCD_REV Num Description T1 LCD_SPL/LCD_SPR pulse width T2 End of LCD_LD of line to beginning of LCD_HSYNC T3 End of LCD_HSYNC to beginning of LCD_LD of line ...
Page 35
LCD_VSYNC LCD_HSYNC LCD_LSCLK LCD_LD[15:0] Num Description T1 LCD_HSYNC to LCD_VSYNC delay T2 LCD_HSYNC pulse width T3 LCD_VSYNC to LCD_LSCLK T4 LCD_LSCLK to LCD_HSYNC Note the LCD_LSCLK period while Tpix is the pixel clock period. LCD_VSYNC, LCD_HSYNC and LCD_LSCLK ...
Page 36
Preliminary Electrical Characteristics TSD THDD TSC ULPI_CLK ULPI_STP (Input) ULPI_DATA (Input-8bit) ULPI_DATA (Input-4bit) TSDD ULPI_DIR/ULPI_NXT (Output) ULPI_DATA (Output-8bit) ULPI_DATA (Output-4bit) Parameter Timing with reference to ULPI_CLK Setup time (control in, 8-bit data in) Setup time (control in, 8-bit data in) ...
Page 37
SSI_BCLK SSI_MCLK STFS SSI_TXD (Output) STFS SSI_RXD (Input) Note: SSI External. Continous clock Synchronous mode only Figure 24. SSI External Continous Clock Timing Diagram Num S1 SSI_BCLK clock period S2 SSI_BCK high-level time S3 SSI_BCK low-level time S4 SSI_BCK rising ...
Page 38
Preliminary Electrical Characteristics Table 21. I Num I1 Start condition hold time I2 Clock low period I3 I2C_SCL/I2C_SDA rise time (V I4 Data hold time I5 I2C_SCL/I2C_SDA fall time (V I6 Clock high time I7 Data setup time I8 Start ...
Page 39
I2 I2C_SCL I1 I2C_SDA 5.16 Fast Ethernet AC Timing Specifications MII signals use TTL signal levels compatible with devices operating at either 5 3.3 V. 5.16.1 MII Receive Signal Timing (FEC_RXD[3:0], FEC_RXDV, FEC_RXER, and FEC_RXCLK) The receiver functions ...
Page 40
Preliminary Electrical Characteristics 5.16.2 MII Transmit Signal Timing (FEC_TXD[3:0], FEC_TXEN, FEC_TXER, FEC_TXCLK) Table 24 lists MII transmit channel timings. The transmitter functions correctly FEC_TXCLK maximum frequency of 25 MHz +1%. There is no minimum frequency requirement. In ...
Page 41
FEC_CRS FEC_COL 5.16.4 MII Serial Management Channel Timing (FEC_MDIO and FEC_MDC) Table 26 lists MII serial management channel timings. The FEC functions correctly with a maximum MDC frequency of 2.5 MHz. Table 26. MII Serial Management Channel Timing Num M10 ...
Page 42
Preliminary Electrical Characteristics 5.17 32-Bit Timer Module Timing Specifications Table 27 lists timer module AC timings. Table 27. Timer Module AC Timing Specifications Name T1 DT0IN / DT1IN / DT2IN / DT3IN cycle time T2 DT0IN / DT1IN / DT2IN ...
Page 43
JTAG and Boundary Scan Timing Num Characteristics J1 TCLK Frequency of Operation J2 TCLK Cycle Period J3 TCLK Clock Pulse Width J4 TCLK Rise and Fall Times J5 Boundary Scan Input Data Setup Time to TCLK Rise J6 Boundary ...
Page 44
Preliminary Electrical Characteristics TCLK V IL Data Inputs Data Outputs Data Outputs Data Outputs TCLK V IL TDI TMS TDO TDO TDO TCLK TRST 5.20 Debug AC Timing Specifications Table 30 lists specifications for the debug AC timing parameters shown ...
Page 45
Num DE0 PSTCLK cycle time DE1 PST valid to PSTCLK high DE2 PSTCLK high to PST invalid DE3 DSCLK cycle time DE4 DSI valid to DSCLK high 1 DE5 DSCLK high to DSO invalid DE6 BKPT input data setup time ...
Page 46
... FB_CLK DE6 BKPT DE7 DSCLK DE3 DSI DSO 6 Revision History Table 31. MCF5329DS Document Revision History Rev. No. 0 • Initial release. 0.1 • Added not to • Added “top view” and “bottom view” where appropriate in mechanical drawings and pinout figures. • Figure ...
Page 47
THIS PAGE INTENTIONALLY LEFT BLANK MCF5329 ColdFire Freescale Semiconductor ® Microprocessor Data Sheet, Rev. 0.1 Preliminary 47 ...
Page 48
... Freescale Semiconductor was negligent regarding the design or manufacture of the part. Freescale™ and the Freescale logo are trademarks of Freescale Semiconductor, Inc. All other product or service names are the property of their respective owners.© Freescale Semiconductor, Inc. 2006. All rights reserved. MCF5329DS Rev. 0.1 03/2006 ...