M24L216128DA-55BEG ESMT [Elite Semiconductor Memory Technology Inc.], M24L216128DA-55BEG Datasheet
M24L216128DA-55BEG
Related parts for M24L216128DA-55BEG
M24L216128DA-55BEG Summary of contents
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... M24L216128DA 2-Mbit (128K x 16) Pseudo Static RAM Functional Description The M24L216128DA is a high-performance CMOS pseudo static RAM (PSRAM) organized as 128K words by 16 bits that supports an asynchronous memory interface. This device features advanced circuit design to provide ultra-low active current. This is ideal for portable applications such as cellular telephones ...
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... CE2 A16 A15 A14 A11 A13 A12 M24L216128DA Publication Date : Jul. 2008 Revision : 1.2 2/14 ...
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... Typical values are included for reference only and are not guaranteed or tested. Typical values are measured at V and ° Elite Semiconductor Memory Technology Inc. Operating I Speed(ns 1MHz Max Typ.[5] Max ensure proper application. SS M24L216128DA Power Dissipation (mA) CC Standby I (µA) SB2 MAX Typ.[5] Max. Typ. [5] Max ...
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... IN =3.6V CC Test Conditions TA = 25° MHz CC(typ) Test Conditions Test conditions follow standard test methods and procedures for measuring thermal impedance, per EIA/ JESD51. M24L216128DA Ambient V CC Temperature ( −25°C to +85°C 2.7V to 3.6V −40°C to +85°C 2.7V to 3.6V -55 -70 Typ Typ ...
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... For the 70-ns cycle, the addresses must SK be stable within 10 ns after the start of the read cycle. Elite Semiconductor Memory Technology Inc. 3. 22000 22000 11000 1.50 Description /I and 30-pF load capacitance M24L216128DA Unit Ω Ω Ω V -55 [14] -70 Min. Max. Min. Max. 55[14 ...
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... Read Cycle Controlled)[14, 16] Notes: 15. Device is continuously selected 16 HIGH for Read Cycle. Elite Semiconductor Memory Technology Inc. -55 Min. Max and CE2 = M24L216128DA -70 Unit Min. Max Publication Date : Jul. 2008 Revision : 1.2 ...
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... Chip Enable goes INACTIVE with WE = HIGH, the output remains in a high-impedance state. 19.During the DON’T CARE period in the DATA I/O waveform, the I/Os are in output state and input signals should not be applied. Elite Semiconductor Memory Technology Inc M24L216128DA Publication Date : Jul. 2008 Revision : 1.2 7/14 ...
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... ESMT Switching Waveforms (continued) Write Cycle Controlled, OE LOW)[18, 19] Write Cycle 4 ( BHE / BLE Controlled, OE LOW)[18, 19] Elite Semiconductor Memory Technology Inc. M24L216128DA Publication Date : Jul. 2008 Revision : 1.2 8/14 ...
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... CE1 WE Address Avoidable Timing 2 CE1 WE Address Elite Semiconductor Memory Technology Inc high (≧tRC) one time at least shown as in Avoidable Timing 2. 15μs ≧ ＜ 15μs ≧ t ≧ RC 15μs ≧ ＜ M24L216128DA t ≧ RC Publication Date : Jul. 2008 Revision : 1.2 9/14 ...
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... Ordering Information Speed (ns) Ordering Code 55 M24L216128DA-55BEG 70 M24L216128DA -70BEG 55 M24L216128DA-55TEG 70 M24L216128DA-70TEG 55 M24L216128DA-55BIG 70 M24L216128DA -70BIG 55 M24L216128DA-55TIG 70 M24L216128DA-70TIG Note: 20.H = Logic HIGH Logic LOW Don’t Care. Elite Semiconductor Memory Technology Inc. Inputs/Outputs BLE X High Z X High Z ...
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... ESMT Package Diagrams Elite Semiconductor Memory Technology Inc. M24L216128DA Publication Date : Jul. 2008 Revision : 1.2 11/14 ...
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... M24L216128DA Dimension in inch Norm Max 0.047 0.006 0.039 0.042 0.018 0.014 0.016 0.008 0.006 0.725 0.730 0.0317 REF 0.463 0.471 0.400 0.4 0.023 0.027 0.031 REF 0.0315 BSC ° 8 Publication Date : Jul. 2008 Revision : 1 ...
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... Add 44-pin TSOPII package 2. Add Avoid timing 2008.02.27 3. Modify type error of function description (standby mode : CE 1 LOW, CE2 HIGH => 1. Move Revision History to the last 2008.07.04 2. Modify voltage range 2.7V~3.3V to 2.7V~3.6V 3. Add Industrial grade M24L216128DA Description CE 1 HIGH, CE2 LOW) Publication Date : Jul. 2008 Revision : 1.2 13/14 ...
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... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Important Notice M24L216128DA Publication Date : Jul. 2008 Revision : 1.2 14/14 ...