M52D128168A-10BG ESMT [Elite Semiconductor Memory Technology Inc.], M52D128168A-10BG Datasheet
M52D128168A-10BG
Related parts for M52D128168A-10BG
M52D128168A-10BG Summary of contents
Page 1
... ESMT Revision History Revision 1.0 (May. 29, 2007) -Original Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 1/47 ...
Page 2
... Elite Semiconductor Memory Technology Inc. Preliminary PRODUCT NO. M52D128168A-7.5TG 133MHz M52D128168A-7.5BG 133MHz M52D128168A-10TG M52D128168A-10BG VSSQ A VSS DQ15 DQ15 V SSQ DQ14 B DQ14 DQ13 DQ13 V DDQ C DQ12 DQ11 DQ12 DQ11 D DQ10 ...
Page 3
... M52D128168A FUNCTIONAL BLOCK DIAGRAM CLK Clock Generator CKE Address CS RAS CAS WE PIN FUNCTION DESCRIPTION PIN NAME CLK System Clock Chip Select CS CKE Clock Enable A0 ~ A11 Address BA0 , BA1 Bank Select Address Row Address Strobe RAS Column Address Strobe CAS Write Enable ...
Page 4
... M52D128168A ABSOLUTE MAXIMUM RATINGS PARAMETER Voltage on any pin relative Voltage on V supply relative Storage temperature Power dissipation Short circuit current Note: Permanent device damage may occur if ABSOLUTE MAXIMUM RATING are exceeded. Functional operation should be restricted to recommended operating condition. Exposure to higher than recommended voltage for extended periods of time could affect device reliability. ...
Page 5
... M52D128168A DC CHARACTERISTICS Recommended operating condition unless otherwise noted， Parameter Symbol Operating Current I CC1 (One Bank Active) Precharge Standby I CC2P Current in power-down I CC2PS mode I CC2N Precharge Standby Current in non power-down mode I CC2NS I CC3P Active Standby Current in power-down mode I CC3PS Active Standby Current ...
Page 6
... M52D128168A AC OPERATING TEST CONDITIONS (V Parameter Input levels (Vih/Vil) Input timing measurement reference level Input rise and fall time Output timing measurement reference level Output load condition 1.8V 13.9K Output VOH(DC) = VDDQ-0.2V, IOH = -0.1mA VOL(DC) = 0.2V, IOL = 0.1mA 10. (Fig.1) DC Output Load circuit OPERATING AC PARAMETER ...
Page 7
... M52D128168A AC CHARACTERISTICS (AC operating conditions unless otherwise noted) Parameter CAS Latency =3 CLK cycle time CAS Latency =2 CAS Latency =3 CLK to valid output delay CAS Latency =2 Output data hold time CLK high pulse width CLK low pulse width Input setup time Input hold time ...
Page 8
... X X Exit Entry Exit Valid , X = Don’t Care Logic High , L = Logic Low ) M52D128168A DQM BA0 WE A10/AP A9~A0 BA1 CODE Row Address L Column ...
Page 9
... Reserved Reserved Reserved Reserved Reserved Reserved M52D128168A Burst Length Burst Length Type Sequential Interleave Reserved Reserved ...
Page 10
... The default value extended mode register is defined as half driving strength and all banks refreshed. Elite Semiconductor Memory Technology Inc. Preliminary PASR DS M52D128168A Address bus Extended Mode Register Set A2-A0 WT=0 000 4Bank 001 2 Bank (BankA& BankB) or (BA1=0) PASR 010 1 Bank (BankA) or ...
Page 11
... M52D128168A Interleave Interleave ...
Page 12
... A7~A8, vendor specific options use A9, A10~A11 and BA1~BA0. A7~A8, A10/AP~A11 and BA0~BA1 must be set to low for normal SDRAM operation. Refer to the table for specific codes for various burst length, burst type and CAS latencies. M52D128168A Publication Date: May. 2007 Revision: 1.0 12/47 ...
Page 13
... Entry to power-down, Auto refresh, Self refresh and Mode register set etc. is possible only when all banks are in idle state. M52D128168A after the last data input to RDL is defined as the minimum number of clock RP ...
Page 14
... The self refresh is exited by restarting the external clock and then asserting high on CKE. This must be followed by NOP’s for a minimum time of t RAS reaches idle state to begin normal operation. with clock cycle RFC M52D128168A before the SDRAM RFC Publication Date: May. 2007 Revision: 1.0 14/47 ...
Page 15
... The DRAM has four banks, each with 4,096 rows. This command activates the bank selected by BA1 and BA0 (BS) and a row address selected by A0 through A11. This command corresponds to a conventional DRAM’s RAS falling. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 15/47 ...
Page 16
... Read command ( CS , CAS = Low, RAS , WE = High) Read data is available after CAS latency requirements have been met. This command sets the burst start address given by the column address. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 16/47 ...
Page 17
... Before executing self refresh, all banks must be precharged. Burst stop command ( Low, RAS , CAS = High) This command terminates the current burst operation. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 17/47 ...
Page 18
... ESMT No operation ( CS = Low , RAS , CAS , WE = High) This command is not a execution command. No operations begin or terminate by this command. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 18/47 ...
Page 19
... M52D128168A ...
Page 20
... M52D128168A ...
Page 21
... Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A D 3 Publication Date: May. 2007 Revision: 1.0 21/47 ...
Page 22
... M52D128168A Publication Date: May. 2007 Revision: 1.0 22/47 ...
Page 23
... M52D128168A ...
Page 24
... determinates the last data write. RDL min delay) with DQM. RAS M52D128168A * ...
Page 25
... from self refresh exit command, any other command can not be accepted. M52D128168A Publication Date: May. 2007 Revision: 1.0 25/47 ...
Page 26
... During read/write burst with auto precharge, RAS interrupt can not be issued. Before the end of burst, new read/write stops read/write burst and starts new read/write burst. During read/write burst with auto precharge, CAS interrupt can not be issued. M52D128168A Publication Date: May. 2007 Revision: 1.0 26/47 ...
Page 27
... NOP (Continue Burst to End ILLEGAL X BA CA, A10/AP ILLEGAL X BA RA, RA10 ILLEGAL ILLEGAL M52D128168A ACTION Row Active) Row Active) Row active Row Active) Row Active) Row active Row Active) Row Active) Row Active) Row Active) Publication Date: May. 2007 Revision: 1.0 Note 2 2 ...
Page 28
... ILLEGAL ILLEGAL ILLEGAL BA = Bank Address CA = Column Address M52D128168A ACTION Idle after tRP Idle after tRP Idle after tRP Row Active after tRCD Row Active after tRCD Idle after tRFC Idle after tRFC Idle after 2clocks Idle after 2clocks AP = Auto Precharge Publication Date: May ...
Page 29
... X X Begin Clock Suspend next cycle Exit Clock Suspend next cycle Maintain Clock Suspend must be satisfy before any command other than exit. SS M52D128168A ACTION Note Idle after tRFC (ABI) 6 Idle after tRFC (ABI) 6 ABI 7 ABI Publication Date: May ...
Page 30
... ESMT Single Bit Read-Write-Read Cycle (Same Page) @ CAS Latency = 3,Burst Length = 1 Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 30/47 ...
Page 31
... Enable auto precharge , precharge bank B at end of burst. 0 Enable auto precharge , precharge bank C at end of burst. 1 Enable auto precharge , precharge bank D at end of burst. Precharge 0 Bank A 1 Bank B 0 Bank C 1 Bank D X All Banks M52D128168A Publication Date: May. 2007 Revision: 1.0 31/47 ...
Page 32
... Issue precharge commands for all banks of the device. 5. Issue 2 or more auto-refresh commands. 6. Issue mode register set command to initialize the mode register. 7. Issue extended mode register set command to set PASR and DS.. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 32/47 ...
Page 33
... Row precharge can interrupt burst on any cycle. [CAS Latency-1] number of valid output data is available after Row precharge. Last valid output will be Hi Output will be Hi-Z after the end of burst. (1,2,4,8 & Full page bit burst) Elite Semiconductor Memory Technology Inc. Preliminary ) after the clock. SHZ M52D128168A Publication Date: May. 2007 Revision: 1.0 33/47 ...
Page 34
... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. Elite Semiconductor Memory Technology Inc. Preliminary before row precharge , will be written. RDL M52D128168A Publication Date: May. 2007 Revision: 1.0 34/47 ...
Page 35
... Note can be don’t cared when RAS , CAS and WE are high at the clock high going edge interrupt a burst read by row precharge, both the read and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 35/47 ...
Page 36
... To interrupt burst write by Row precharge , DQM should be asserted to mask invalid input data interrupt burst write by Row precharge , both the write and the precharge banks must be the same. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 36/47 ...
Page 37
... ESMT Read & Write Cycle at Different Bank @ Burst Length = 4 *Note : 1. t should be met to complete write. CDL Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 37/47 ...
Page 38
... ESMT Read & Write cycle with Auto Precharge @ Burst Length = 4 *Note : 1. t should be controlled to meet minimum t CDL (In the case of Burst Length = 1 & 2) Elite Semiconductor Memory Technology Inc. Preliminary before internal precharge start. RAS M52D128168A Publication Date: May. 2007 Revision: 1.0 38/47 ...
Page 39
... ESMT Clock Suspension & DQM Operation Cycle @ CAS Letency = 2 , Burst Length = 4 *Note : 1. DQM is needed to prevent bus contention Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 39/47 ...
Page 40
... Both cases are illustrated above timing diagram. See the label 1,2 on them. But at burst write, Burst stop and RAS interrupt should be compared carefully. Refer the timing diagram of “Full page write burst stop cycles”. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 40/47 ...
Page 41
... DQM should mask invalid input data on precharge command cycle when asserting precharge before end of burst. Input data after Row precharge cycle will be masked internally. 2. Burst stop is valid at every burst length. Elite Semiconductor Memory Technology Inc. Preliminary M52D128168A Publication Date: May. 2007 Revision: 1.0 41/47 ...
Page 42
... Both banks should be in idle state prior to entering precharge power down mode. 2. CKE should be set high at least 1CLK + t 3. Can not violate minimum refresh specification. (64ms) Elite Semiconductor Memory Technology Inc. Preliminary prior to Row active command. SS M52D128168A Publication Date: May. 2007 Revision: 1.0 42/47 ...
Page 43
... CKE going high to complete self refresh exit. RFC 7. Burst auto refresh is required before self refresh entry and after self refresh exit if the system uses burst refresh. Elite Semiconductor Memory Technology Inc. Preliminary is required before exit from self refresh. RAS M52D128168A Publication Date: May. 2007 Revision: 1.0 43/47 ...
Page 44
... CS , RAS , CAS , & WE activation at the same clock cycle with address key will set internal mode register. 2. Minimum 2 clock cycles should be met before new RAS activation. 3. Please refer to Mode Register Set table. Elite Semiconductor Memory Technology Inc. Preliminary Extended Mode Register Set Cycle M52D128168A Publication Date: May. 2007 Revision: 1.0 44/47 ...
Page 45
... D 22.22 BSC E 11.76 BSC 10.16 BSC L 0.40 0.50 0.60 0.016 0.020 0.024 0.80 REF e 0.80 BSC Θ 0° 10° M52D128168A SEE DETAIL 0.21 REF 0.665 REF A 1 -C- DETAIL "A" SECTION B-B Dimension in inch Min Norm Max 0.047 0.018 0.008 ...
Page 46
... Elite Semiconductor Memory Technology Inc. Preliminary Dimension in mm Dimension in inch Min Norm Max Min 1.00 0.20 0.25 0.30 0.008 0.61 0.66 0.71 0.024 0.30 0.35 0.40 0.012 7.90 8.00 8.10 0.311 7.90 8.00 8.10 0.311 6.40 6.40 0.80 M52D128168A Norm Max 0.039 0.010 0.012 0.026 0.028 0.014 0.016 0.315 0.319 0.315 0.319 0.252 0.252 0.031 Publication Date: May. 2007 Revision: 1.0 46/47 ...
Page 47
... If products described here are to be used for such kinds of application, purchaser must do its own quality assurance testing appropriate to such applications. Elite Semiconductor Memory Technology Inc. Preliminary Important Notice M52D128168A Publication Date: May. 2007 Revision: 1.0 47/47 ...