24C65 MicrochipTechnology, 24C65 Datasheet - Page 5

• Manufacturer Part Number: 24C65
• Description: 64K5.0VI2CSmartSerialEEPROM
• Manufacturer: MicrochipTechnology

3.6
A control byte is the first byte received following the start
condition from the master device. The control byte con-
sists of a four bit control code, for the 24C65 this is set
as 1010 binary for read and write operations. The next
three bits of the control byte are the device select bits
(A2, A1, A0). They are used by the master device to
select which of the eight devices are to be accessed.
These bits are in effect the three most significant bits of
the word address. The last bit of the control byte (R/W)
defines the operation to be performed. When set to a one
a read operation is selected, when set to a zero a write
operation is selected. The next two bytes received define
the address of the first data byte (Figure 4-1). Because
only A12..A0 are used, the upper three address bits
must be zeros. The most significant bit of the most signif-
icant byte is transferred first. Following the start condi-
tion, the 24C65 monitors the SDA bus checking the
device type identifier being transmitted. Upon receiving a
1010 code and appropriate device select bits, the slave
device (24C65) outputs an acknowledge signal on the
SDA line. Depending upon the state of the R/W bit, the
24C65 will select a read or write operation.
FIGURE 3-2:
FIGURE 4-1:
SDA LINE
Operation
BUS ACTIVITY
MASTER
BUS ACTIVITY
1996 Microchip Technology Inc.
Read
Write
1
START
Device Addressing
0
Control
SLAVE ADDRESS
Code
1010
1010
1
CONTROL BYTE
ALLOCATION
BYTE WRITE
S
S
T
A
R
T
0
Device Address
Device Address
Device Select
CONTROL
A2
This document was created with FrameMaker 4 0 4
READ/WRITE
BYTE
A1
R/W
A0
R/W
1
0
A
A
C
K
0 0
0
ADDRESS
WORD
4.0
4.1
Following the start condition from the master, the control
code (four bits), the device select (three bits), and the
R/W bit which is a logic low is placed onto the bus by the
master transmitter. This indicates to the addressed slave
receiver (24C65) that a byte with a word address will fol-
low after it has generated an acknowledge bit during the
ninth clock cycle. Therefore the next byte transmitted by
the master is the high-order byte of the word address
and will be written into the address pointer of the 24C65.
The next byte is the least significant address byte. After
receiving another acknowledge signal from the 24C65
the master device will transmit the data word to be writ-
ten into the addressed memory location. The 24C65
acknowledges again and the master generates a stop
condition. This initiates the internal write cycle, and dur-
ing this time the 24C65 will not generate acknowledge
signals (Figure 4-1).
4.2
The write control byte, word address and the first data
byte are transmitted to the 24C65 in the same way as in
a byte write. But instead of generating a stop condition
the master transmits up to eight pages of eight data
bytes each (64 bytes total) which are temporarily stored
in the on-chip page cache of the 24C65. They will be
written from the cache into the EEPROM array after the
master has transmitted a stop condition. After the receipt
of each word, the six lower order address pointer bits are
internally incremented by one. The higher order seven
bits of the word address remain constant. If the master
should transmit more than eight bytes prior to generating
the stop condition (writing across a page boundary), the
address counter (lower three bits) will roll over and the
pointer will be incremented to point to the next line in the
cache. This can continue to occur up to eight times or
until the cache is full, at which time a stop condition
should be generated by the master. If a stop condition is
not received, the cache pointer will roll over to the first
line (byte 0) of the cache, and any further data received
will overwrite previously captured data. The stop condi-
tion can be sent at any time during the transfer. As with
the byte write operation, once the stop condition is
received an internal write cycle will begin. The 64 byte
cache will continue to capture data until a stop condition
occurs or the operation is aborted (Figure 4-2).
WRITE OPERATION
Byte Write
Page Write
A
C
K
DATA
DS21058G-page 5
24C65
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