24C65 MicrochipTechnology, 24C65 Datasheet - Page 7

• Manufacturer Part Number: 24C65
• Description: 64K5.0VI2CSmartSerialEEPROM
• Manufacturer: MicrochipTechnology

5.0
Read operations are initiated in the same way as write
operations with the exception that the R/W bit of the
slave address is set to one. There are three basic types
of read operations: current address read, random read,
and sequential read.
5.1
The 24C65 contains an address counter that maintains
the address of the last word accessed, internally incre-
mented by one. Therefore, if the previous access (either
a read or write operation) was to address n (n is any
legal address), the next current address read operation
would access data from address n + 1. Upon receipt of
the slave address with R/W bit set to one, the 24C65
issues an acknowledge and transmits the eight bit data
word. The master will not acknowledge the transfer but
does generate a stop condition and the 24C65 discon-
tinues transmission (Figure 4-3).
5.2
Random read operations allow the master to access
any memory location in a random manner. To perform
this type of read operation, first the word address must
be set. This is done by sending the word address to the
24C65 as part of a write operation (R/W bit set to 0).
After the word address is sent, the master generates a
start condition following the acknowledge. This termi-
nates the write operation, but not before the internal
address pointer is set. Then the master issues the con-
trol byte again but with the R/W bit set to a one. The
24C65 will then issue an acknowledge and transmit the
eight bit data word. The master will not acknowledge
the transfer but does generate a stop condition which
causes the 24C65 to discontinue transmission
(Figure 4-4).
5.3
Sequential reads are initiated in the same way as a ran-
dom read except that after the 24C65 transmits the first
data byte, the master issues an acknowledge as
opposed to the stop condition used in a random read.
This acknowledge directs the 24C65 to transmit the
next sequentially addressed 8 bit word (Figure 4-5).
Following the final byte transmitted to the master, the
master will NOT generate an acknowledge but will gen-
erate a stop condition.
To provide sequential reads the 24C65 contains an
internal address pointer which is incremented by one at
the completion of each operation. This address pointer
allows the entire memory contents to be serially read
during one operation.
1996 Microchip Technology Inc.
READ OPERATION
Current Address Read
Random Read
Sequential Read
5.4
The device select bits A2, A1, A0 can be used to
expand the contiguous address space for up to 512K
bits by adding up to eight 24C65's on the same bus. In
this case, software can use A0 of the control byte as
address bit A13, A1 as address bit A14, and A2 as
address bit A15.
5.5
The SCL and SDA inputs have filter circuits which sup-
press noise spikes to assure proper device operation
even on a noisy bus. All I/O lines incorporate Schmitt
triggers for 400 KHz (Fast Mode) compatibility.
5.6
The location of the high-endurance block within the
memory map is programmed by setting the leading bit
7 (S/HE) of the configuration byte to 0. The upper bits
of the address loaded in this command will determine
which 4K block within the memory map will be set to
high endurance (Figure 8-1). This block will be capable
of 10,000,000 erase/write cycles.
5.7
The 24C65 has a sophisticated mechanism for
write-protecting portions of the array. This write protect
function is programmable and allows the user to protect
0-15 contiguous 4K blocks. The user sets the security
option by sending to the device the starting block num-
ber for the protected region and the number of blocks to
be protected. If the security option is invoked with 0
blocks protected, then all portions of the array will be
unprotected. All parts will come from the factory in the
default configuration with the starting block number set
to 15 and the number of protected blocks set to zero.
THE SECURITY OPTION CAN BE SET ONLY ONCE.
To invoke the security option, a write command is sent
to the device with the leading bit (bit 7) of the first
address byte set to a 1 (Figure 8-1). Bits 1-4 of the first
address byte define the starting block number for the
protected region. For example, if the starting block
number is to be set to 5, the first address byte would be
1XX0101X. Bits 0, 5 and 6 of the first address byte are
disregarded by the device and can be either high or low.
The device will acknowledge after the first address
byte. A byte of don't care bits is then sent by the master,
with the device acknowledging afterwards. The third
byte sent to the device has bit 7 (S/HE) set high and bit
6 (R) set low. Bits 4 and 5 are don't cares and bits 0-3
Note:
Contiguous Addressing Across
Multiple Devices
Noise Protection
High Endurance Block
Security Options
The High Endurance Block cannot be
changed after the security option has been
set. If the H.E. block is not programmed by
the user, the default location is the highest
block of memory.
DS21058G-page 7
24C65