T89C51CC01 Atmel, T89C51CC01 Datasheet - Page 24
T89C51CC01
Manufacturer Part Number
T89C51CC01
Description
Enhanced 8-Bit Microcontroller
Manufacturer
Atmel
Datasheet
1.T89C51CC01.pdf
(170 pages)
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Figure 9. Power-down Exit Waveform Using INT1:0#
24
T89C51CC01
INT1:0#
OSC
Active phase
2. Generate a reset.
Notes:
–
2. Exit from power-down by reset redefines all the SFRs, but does not affect the internal
A logic high on the RST pin clears PD bit in PCON register directly and
asynchronously. This starts the oscillator and restores the clock to the CPU
and peripherals. Program execution momentarily resumes with the
instruction immediately following the instruction that activated Power-down
mode and may continue for a number of clock cycles before the internal
reset algorithm takes control. Reset initializes the T89C51CC01 and vectors
the CPU to address 0000h.
1. During the time that execution resumes, the internal RAM cannot be accessed; how-
Power-down phase
ever, it is possible for the Port pins to be accessed. To avoid unexpected outputs at
the Port pins, the instruction immediately following the instruction that activated the
Power-down mode should not write to a Port pin or to the external RAM.
RAM content.
Oscillator restart phase
Active phase
4129K–CAN–01/05
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