SAA4974 Philips, SAA4974 Datasheet - Page 12

• Manufacturer Part Number: SAA4974
• Description: Besic without ADC
• Manufacturer: Philips

Philips Semiconductors
7.1.4
The Y samples can be shifted onto 8 positions with
reference to the UV samples. This shift is meant to account
for a possible difference in delay previous to the
SAA4974H. The zero delay setting is suitable for the
nominal case of aligned input data according to the
interface format standard. The other settings provide one
to seven samples less delay in Y.
7.1.5
Sidepanels are generated by switching Y and the 4 MSB
of U and V to certain programmable values. The start and
stop values for the sidepanels with reference to the rising
edge of the HRD signal are programmable in a resolution
of 4 LLD clock cycles. In addition a fine shift of 0 to 3 LLD
clock cycles of both values can be achieved.
Blanking is done by switching Y to value 64 at 10-bit word
and UV to value 0 (in twos complement). Blanking is
controlled by a composite signal HVBDA, existing of a
horizontal part HBDA and a vertical part VBDA. Set and
reset value of the horizontal control signal HBDA are
programmable with reference to the rising edge of the
HRD signal, set and reset value of the vertical control
1998 Apr 21
Besic without ADC
IH_PeakingI
(1)
(2)
(3)
(4)
Fig.9
handbook, halfpage
(dB)
=
=
=
= 0.
Y-
S
1
1
1
2
4
8
IDEPANELS AND BLANKING
Peaking transfer function with variation of
( =
DELAY
.
.
.
16
14
12
10
8
6
4
2
0
0
1
2
).
1/4f s
(1)
(2)
(3)
(4)
MGE099
1/2f s
12
signal VBDA are programmable with reference to the
rising edge of the VA signal.
The range of the Y output signal can be selected between
9 and 10 bits. In case of 9 bits for the nominal signal there
is room left for under and overshoot (adding up to a total of
10 bits). In case of selecting all 10 bits of the luminance
Digital-to-Analog Converter (DAC) for the nominal signal
any under or overshoot will be clipped. In case of selecting
9 bits of the luminance DAC for the nominal signal under
or overshoots are limited within a programmable range
(see Fig.12).
7.2
Three identical 10-bit DACs are used to map the 4 : 4 : 4
data to analog levels.
7.3
The SAA4974H contains an embedded
80C51 microprocessor core including 256 byte RAM and
16 kbyte ROM. The microprocessor runs on a 16 MHz
clock, generated by dividing the 32 MHz display clock by a
factor of 2. For controlling internal registers a host
interface, consisting of a parallel address and data bus, is
IH_PeakingI
(1)
(2)
(3)
Fig.10 Peaking transfer function with variation of
handbook, halfpage
(dB)
Digital-to-analog conversion
Microprocessor
=
=
=
1
1
1
12
10
2
4
8
( = 0).
8
6
4
2
0
.
.
.
0
1/4f s
(1)
(2)
(3)
Product specification
SAA4974H
MGE100
1/2f s