SAA4974 Philips, SAA4974 Datasheet - Page 15

• Manufacturer Part Number: SAA4974
• Description: Besic without ADC
• Manufacturer: Philips

Philips Semiconductors
7.8
Note
1. Detailed information about the software dependent I
1998 Apr 21
Subaddress 00H to 35H: reserved; note 1
Subaddress 36H and 37H (DCTI)
36H
37H
Subaddress 3AH and 3BH (sidepanels overlay)
3AH
3BH
Subaddress 3CH (peaking)
3CH
Subaddress 3DH to 3FH (sidepanel position)
3DH
3EH
3FH
ADDRESS
Besic without ADC
register specification of the SAA4974H” (AN97042).
I
2
C-bus control registers
0 to 2
3 to 6
7
0 and 1 dcti_limit
2
3
4
5
6 and 7
0 to 3
4 to 7
0 to 7
0 and 1 peak_
2 and 3 peak_
4 and 5 peak_limit
6 and 7 peak_coring
0 to 7
0 to 7
0 and 1 sidepanel_fdel
2
3
4 to 6
7
BIT
dcti_gain
dcti_threshold
dcti_ddx_sel
dcti_separate
dcti_protection
dcti_filteron
dcti_superhill
overlay_u
overlay_v
overlay_y
sidepanel_start sidepanel start position (8 MSB) with reference to the rising edge of
sidepanel_stop sidepanel stop position (8 MSB) with reference to the rising edge of
display_mode
uv_inv
ydelay_out
en_hdsp_rst
NAME
DCTI gain: 0, 1, 2, 3, 4, 5, 6 and 7
DCTI threshold: 0 and 1 to 15
DCTI selection of first differentiating filter; see Fig.3
DCTI limit for pixel shift range: 0, 1, 2 and 3
DCTI separate processing of U and V signals; 0 = off and 1 = on
DCTI over the hill protection; 0 = off and 1 = on
DCTI post-filter; 0 = off and 1 = on
DCTI super hill mode; 0 = off and 1 = on
reserved
sidepanels overlay U (4 MSB)
sidepanels overlay V (4 MSB)
sidepanels overlay Y (8 MSB)
peaking settings : 0,
peaking settings : 0,
peaking limiter settings in display mode = 0:
(256/767, 171/852, 86/937 and 0/1023)
peaking coring settings: 0, +1/ 2, +3/ 4 and +7/ 8 LSB at 8-bit word
HRD signal
HRD signal
fine delay of sidepanel signal in LLD clock cycles: (0, 1, 2 and 3)
display mode (display mode = 0: 9-bit for the nominal output signal,
black level 288 and white level 767; display mode = 1: 10-bit for the nominal
output signal, black level 64 and white level 1023)
inverts UV input signals: 0 = no inversion, 1 = inversion
variable Y-delay in LLD clock cycles: 7, 6, 5, 4, 3, 2, 1 and 0
enable hdsp reset: 0 = disable and 1 = enable
2
C-bus registers can be found in Application Note “I
15
1
1
8
8
,
,
1
1
4
4
and
and
DESCRIPTION
1
1
2
2
Product specification
SAA4974H
2
C-bus