PSD913F1-B-90JI ST Microelectronics, PSD913F1-B-90JI Datasheet - Page 70

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PSD913F1-B-90JI

Manufacturer Part Number
PSD913F1-B-90JI
Description
Flash In-System Programmable ISP Peripherals For 8-bit MCUs
Manufacturer
ST Microelectronics
Datasheet
PSD9XX Family
66
NOTE: 1. Reset input has hysteresis. V
Symbol
V
V
V
V
V
V
V
V
V
V
V
I
I
V
I
I
I
SBY
IDLE
SB
LI
LO
CC
IH
IL
IH1
IL1
HYS
LKO
OL
OH
OH 1
SBY
DF
2. CSI deselected or internal Power Down mode is active.
3. PLD is in non-turbo mode and none of the inputs are switching
4. Refer to Figure 32 for PLD current calculation.
5. I
OUT
Supply Voltage
High Level Input Voltage
Low Level Input Voltage
Reset High Level Input Voltage
Reset Low Level Input Voltage
Reset Pin Hysteresis
V
Output Low Voltage
Output High Voltage Except V
Output High Voltage V
SRAM Standby Voltage
SRAM Standby Current (V
Idle Current (V
SRAM Data Retention Voltage
Standby Supply Current for Power
Down Mode
Input Leakage Current
Output Leakage Current
= 0 mA
CC
Min for Flash Erase and Program
Parameter
STBY
Pin)
STBY
IL1
is valid at or below .2V
STBY
On
STBY
Pin)
On
All Speeds
4.5 V < V
4.5 V < V
(Note 1)
(Note 1)
I
I
I
I
I
V
V
Only on V
CSI > V
(Notes 2 and 3)
V
0.45 < V
PLD_TURBO = OFF,
OL
OL
OH
OH
OH 1
CC
CC
SS
CC
= 20 µA, V
= 8 mA, V
= –20 µA, V
= –2 mA, V
< V
= 0 V
> V
= 1 µA
–.1. V
CC
IN
SBY
IN
CC
CC
STBY
< V
Conditions
< V
–0.3 V
IH1
< 5.5 V
< 5.5 V
CC
CC
CC
CC
is valid at or above .8V
CC
CC
= 4.5 V
= 4.5 V
= 4.5 V
= 4.5 V
V
SBY
.8 V
–0.1
–10
4.5
–.5
–.5
0.3
2.5
4.4
2.4
2.0
–1
Min
2
2
– 0.8
CC
CC
.
Typ
0.01
0.25
4.49
3.9
0.5
±.1
± 5
75
5
Preliminary Information
.2 V
V
V
Max
CC
CC
0.45
V
200
5.5
0.8
4.2
0.1
0.1
10
CC
1
1
CC
+.5
+.5
–.1
Unit
µA
µA
µA
µA
µA
V
V
V
V
V
V
V
V
V
V
V
V
V
V

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