W49V002FAQ Winbond, W49V002FAQ Datasheet
W49V002FAQ
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W49V002FAQ Summary of contents
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... FWH bus interface mode the Programmer interface mode, it acts like the traditional flash but with a multiplexed address inputs. But in the FWH interface mode, this device complies with the Intel FWH specification. The device can also be programmed and erased using standard EPROM programmers ...
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PIN CONFIGURATIONS ...
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... FWH mode. In Programmer mode, this device just behaves like traditional flash parts with 8 data lines. But the row and column address inputs are multiplexed, which go through address inputs A[10:0]. For FWH mode, It complies with the FWH Interface Specification ...
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Program Operation The W49V002FA is programmed on a byte-by-byte basis. Program operation can only change logical data "1" to logical data "0." The erase operation, which changed entire data in main memory and/or boot block from "0" to "1", is ...
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Toggle Bit (DQ )- Write Status Detection 6 In addition to data polling, the W49V002FA provides another method for determining the end of a program cycle. During the internal program or erase cycle, any consecutive attempts to read DQ produce ...
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Operating Mode Selection - FWH Mode Operation modes in FWH interface mode are determined by "START Cycle" when it is selected. When it is not selected, its outputs (FWH[3:0]) will be disable. Please reference to the "FWH Cycle Definition". TABLE ...
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FWH CYCLE DEFINITION FIELD NO. OF CLOCKS START 1 "1101b" indicates FWH Memory Read cycle; while "1110b" indicates FWH Memory Write cycle. IDSEL 1 This one clock field indicates which FWH component is being selected. MSIZE 1 Memory Size. There ...
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Embedded Programming Algorithm Increment Address Program Command Sequence (Address/Command): Start Write Program Command Sequence (see below) #Data Polling/ Toggle bit No Last Address ? Yes Programming Completed 5555H/AAH 2AAAH/55H 5555H/A0H Program Address/Program Data - 8 - W49V002FA Pause T BP ...
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Embedded Erase Algorithm Chip Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH 2AAAH/55H 5555H/10H Start Write Erase Command Sequence (see below) #Data Polling or Toggle Bit Successfully Completed Erasure Completed Individual Sector Erase Command Sequence (Address/Command): 5555H/AAH 2AAAH/55H 5555H/80H 5555H/AAH ...
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Embedded #Data Polling Algorithm Embedded Toggle Bit Algorithm Start VA = Byte address for programming Read Byte (DQ0 - DQ7) Address = VA No DQ7 = Data ? Yes Pass Start Read Byte (DQ0 - DQ7) Address = Don't Care ...
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Software Product Identification and Boot Block Lockout Detection Acquisition Flow Product Identification Entry (1) Load data AA to address 5555 Load data 55 to address 2AAA Load data 90 to address 5555 Pause 10 S Notes for software product identification/boot ...
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Boot Block Lockout Enable Acquisition Flow Boot Block Lockout Feature Set Flow Load data AA to address 5555 Load data 55 to address 2AAA Load data 80 to address 5555 Load data AA to address 5555 Load data 55 to ...
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DC CHARACTERISTICS Absolute Maximum Ratings PARAMETER Power Supply Voltage Operating Temperature Storage Temperature D.C. Voltage on Any Pin to Ground Potential Transient Voltage (<20 nS) on Any Pin to Ground Potential Note: Exposure to conditions beyond those ...
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FWH interface Mode DC Operating Characteristics ( GND A PARAMETER SYM. Power Supply I CC Current Standby Current I 1 FWH4 = 0 Standby ...
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PROGRAMMER INTERFACE MODE AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Time Input/Output Timing Level Output Load AC Test Load and Waveform D OUT 30 pF (Including Jig and Scope) CONDITIONS < ...
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Programmer Interface Mode AC Characteristics, continued AC Characteristics Read Cycle Timing Parameters (V = 3. GND A PARAMETER Read Cycle Time Row/Column Address Set Up Time Row/Column Address Hold ...
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TIMING WAVEFORMS FOR PROGRAMMER INTERFACE MODE Read Cycle Timing Diagram #RESET T RST A[10: #WE #OE High-Z DQ[7:0] Write Cycle Timing Diagram T RST #RESET A[10:0] Column Address #OE #WE DQ[7: ...
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Timing Waveforms for Programmer Interface Mode, continued Program Cycle Timing Diagram A[10:0] (Internal A[17:0]) DQ[7: #OE #WE Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal address. ...
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Timing Waveforms for Programmer Interface Mode, continued Toggle Bit Timing Diagram A[10: #WE #OE DQ6 Boot Block Lockout Enable Timing Diagram A[10:0] 5555 (Internal A[17:0]) DQ[7: # #WE SB0 Note: The internal address A[17:0] ...
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Timing Waveforms for Programmer Interface Mode, continued Chip Erase Timing Diagram A[10:0] 5555 (Internal A[17:0]) DQ[7: #OE #WE Note: The internal address A[17:0] are converted from external Column/Row address. Column/Row Address are mapped to the Low/High order internal ...
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FWH INTERFACE MODE AC CHARACTERISTICS AC Test Conditions PARAMETER Input Pulse Levels Input Rise/Fall Slew Rate Input/Output Timing Level Output Load AC Test Load and Waveform D OUT Test when output from low to high Read/Write Cycle ...
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TIMING WAVEFORMS FOR FWH INTERFACE MODE Read Cycle Timing Diagram CLK #RESET FWH4 Start FWH IDSEL Read FWH[3:0] 1101b XXXXb XA[22]XXb XXA[17:16] 0000b 1 Clock 1 Clock Note: When A22 = high, the host will read ...
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Timing Waveforms for FWH Interface Mode, continued Program Cycle Timing Diagram CLK #RESET FWH4 1st Start IDSEL FWH[3:0 ] XXXXb 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 2nd Start IDSEL FWH[3:0 ] XXXXb 1110b 0000b 1 Clock 1 ...
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Timing Waveforms for FWH Interface Mode, continued #DATA Polling Timing Diagram CLK #RESET FWH4 Start IDSEL FWH[3:0] XXXXb 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 Start IDSEL FWH[3:0] XXXXb 0000b 1101b 1 Clock 1 Clock CLK #RESET FWH4 ...
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Timing Waveforms for FWH Interface Mode, continued Toggle Bit Timing Diagram CLK #RESET FWH4 Start IDSEL FWH[3:0] XXXXb 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 Start IDSEL FWH[3:0] 0000b 1101b XXXXb 1 Clock 1 Clock CLK #RESET FWH4 ...
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Timing Waveforms for FWH Interface Mode, continued Boot Block Lockout Enable Timing Diagram CLK #RESET FWH4 IDSEL 1st Start FWH[3:0] 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 2nd Start IDSEL FWH[3:0] XXXXb 1110b 0000b 1 Clock 1 Clock ...
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Timing Waveforms for FWH Interface Mode, continued Chip Erase Timing Diagram CLK #RESET FWH4 IDSEL 1st Start XXXXb FWH[3:0] 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 IDSEL 2th Start FWH[3:0] XXXXb 1110b 0000b 1 Clock 1 Clock CLK ...
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Timing Waveforms for FWH Interface Mode, continued Sector Erase Timing Diagram CLK #RESET FWH4 1st Start IDSEL 0000b FWH[3:0] 1110b 1 Clock 1 Clock CLK #RESET FWH4 2nd Start IDSEL FWH[3:0] 1110b 0000b 1 Clock 1 Clock CLK #RESET FWH4 ...
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Timing Waveforms for FWH Interface Mode, continued FGPI Register/Product ID Readout Timing Diagram CLK #RESET FWH4 IDSEL Start FWH[3:0] 1101b 0000b A[27:24] Load Address "FFBC0100(hex)" Clocks for GPI Register 1 Clock 1 Clock & "FFBC0000(hex)/FFBC0001(hex) for Product ID ...
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... PART NO. ACCESS TIME (nS) W49V002FAP 11 W49V002FAQ 11 Notes: 1. Winbond reserves the right to make changes to its products without prior notice. 2. Purchasers are responsible for performing appropriate quality assurance testing on products intended for use in applications where personal injury might occur as a consequence of product failure. HOW TO READ THE TOP MARKING ...
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... Dimensions D & not include interlead flash. 2. Dimension b1 does not include dambar protrusion/intrusion. 3. Controlling dimension: Inches 4. General appearance spec. should be based on final visual inspection sepc. Dimension in Inches Dimension in mm Symbol Min. Nom. Max. Min. Nom. Max. ...
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... DD to DD; IH DD. for the #INIT pin input spec. Winbond Electronics (Shanghai) Ltd. 27F, 2299 Yan An W. Rd. Shanghai, 200336 China TEL: 86-21-62365999 FAX: 86-21-62365998 Winbond Electronics (H.K.) Ltd. Unit 9-15, 22F, Millennium City, No. 378 Kwun Tong Rd., Kowloon, Hong Kong TEL: 852-27513100 FAX: 852-27552064 ...