ISPLSI2128E100LT176 Lattice Semiconductor Corp., ISPLSI2128E100LT176 Datasheet

ISPLSI2128E100LT176

Manufacturer Part Number

ISPLSI2128E100LT176

Description

QFP176

Manufacturer

Lattice Semiconductor Corp.

Datasheet

1.ISPLSI2128E100LT176.pdf (11 pages)

Specifications of ISPLSI2128E100LT176

Date_code

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LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

2128e_03

• SUPERFAST HIGH DENSITY IN-SYSTEM

• HIGH PERFORMANCE E

• ispLSI OFFERS THE FOLLOWING ADDED FEATURES

• OFFERS THE EASE OF USE AND FAST SYSTEM

Features

PROGRAMMABLE LOGIC

— 6000 PLD Gates

— 128 I/O Pins, Eight Dedicated Inputs

— 128 Registers

— High Speed Global Interconnect

— Wide Input Gating for Fast Counters, State

— Small Logic Block Size for Random Logic

— 100% Functional/JEDEC Upward Compatible with

—

— TTL Compatible Inputs and Outputs

— 5V Programmable Logic Core

— ispJTAG™ In-System Programmable via IEEE 1149.1

— User-Selectable 3.3V or 5V I/O Supports Mixed-

— PCI Compatible Outputs

— Open-Drain Output Option

— Electrically Erasable and Reprogrammable

— Non-Volatile

— Unused Product Term Shutdown Saves Power

— Increased Manufacturing Yields, Reduced Time-to-

— Reprogram Soldered Devices for Faster Prototyping

SPEED OF PLDs WITH THE DENSITY AND FLEXIBILITY

OF FIELD PROGRAMMABLE GATE ARRAYS

— Complete Programmable Device Can Combine Glue

— Enhanced Pin Locking Capability

— Three Dedicated Clock Input Pins

— Synchronous and Asynchronous Clocks

— Programmable Output Slew Rate Control to

— Flexible Pin Placement

— Optimized Global Routing Pool Provides Global

Machines, Address Decoders, etc.

ispLSI 2128 Devices

(JTAG) Test Access Port

Voltage Systems

Market and Improved Product Quality

Logic and Structured Designs

Minimize Switching Noise

Interconnectivity

max = 180 MHz Maximum Operating Frequency

pd = 5.0 ns Propagation Delay

CMOS

TECHNOLOGY

The ispLSI 2128E is a High Density Programmable Logic

Device. The device contains 128 Registers, 128 Univer-

sal I/O pins, eight Dedicated Input pins, three Dedicated

Clock Input pins, two dedicated Global OE input pins and

a Global Routing Pool (GRP). The GRP provides com-

plete interconnectivity between all of these elements.

The ispLSI 2128E features 5V in-system programmabil-

ity and in-system diagnostic capabilities. The ispLSI

2128E offers non-volatile reprogrammability of all logic,

as well as the interconnect to provide truly reconfigurable

systems.

The basic unit of logic on the ispLSI 2128E device is the

Generic Logic Block (GLB). The GLBs are labeled A0, A1

.. D7 (see Figure 1). There are a total of 32 GLBs in the

ispLSI 2128E device. Each GLB is made up of four

macrocells. Each GLB has 18 inputs, a programmable

AND/OR/Exclusive OR array, and four outputs which can

be configured to be either combinatorial or

registered.Inputs to the GLB come from the GRP and

dedicated inputs. All of the GLB outputs are brought back

into the GRP so that they can be connected to the inputs

of any GLB on the device.

The device also has 128 I/O cells, each of which is

directly connected to an I/O pin. Each I/O cell can be

Functional Block Diagram

Description

Output Routing Pool (ORP)

SuperFAST™ High Density PLD

Global Routing Pool (GRP)

ispLSI

In-System Programmable

Logic

Array

Output Routing Pool (ORP)

2128E

GLB

January 2002

0139(9A)/2128

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