GAL22LV10D-5LJ Lattice Semiconductor Corp., GAL22LV10D-5LJ Datasheet

GAL22LV10D-5LJ

Manufacturer Part Number

GAL22LV10D-5LJ

Description

Manufacturer

Lattice Semiconductor Corp.

Datasheets

1.GAL22LV10.pdf (19 pages)

2.GAL22LV10D-5LJ.pdf (18 pages)

Specifications of GAL22LV10D-5LJ

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Download datasheet (332Kb)

• HIGH PERFORMANCE E

• 3.3V LOW VOLTAGE 22V10 ARCHITECTURE

• ACTIVE PULL-UPS ON ALL PINS (GAL22LV10D)

• E

• TEN OUTPUT LOGIC MACROCELLS

• PRELOAD AND POWER-ON RESET OF ALL REGISTERS

• APPLICATIONS INCLUDE:

• ELECTRONIC SIGNATURE FOR IDENTIFICATION

• LEAD-FREE PACKAGE OPTIONS

The GAL22LV10D, at 4 ns maximum propagation delay time, pro-

vides the highest speed performance available in the PLD market.

The GAL22LV10C can interface with both 3.3V and 5V signal levels.

The GAL22LV10 is manufactured using Lattice Semiconductor's

advanced 3.3V E

Electrically Erasable (E

times (<100ms) allow the devices to be reprogrammed quickly and

efficiently.

The generic architecture provides maximum design flexibility by

allowing the Output Logic Macrocell (OLMC) to be configured by

the user.

Unique test circuitry and reprogrammable cells allow complete AC,

DC, and functional testing during manufacture. As a result, Lattice

Semiconductor delivers 100% field programmability and function-

ality of all GAL products. In addition, 100 erase/write cycles and

data retention in excess of 20 years are specified.

to change without notice.

LATTICE SEMICONDUCTOR CORP., 5555 Northeast Moore Ct., Hillsboro, Oregon 97124, U.S.A.

Tel. (503) 268-8000; 1-800-LATTICE; FAX (503) 268-8556; http://www.latticesemi.com

22lv10_06

Features

Description

— 4 ns Maximum Propagation Delay

— Fmax = 250 MHz

— 3 ns Maximum from Clock Input to Data Output

— UltraMOS

— JEDEC-Compatible 3.3V Interface Standard

— 5V Compatible Inputs

— I/O Interfaces with Standard 5V TTL Devices

— Reconfigurable Logic

— Reprogrammable Cells

— 100% Tested/100% Yields

— High Speed Electrical Erasure (<100ms)

— 20 Year Data Retention

— Maximum Flexibility for Complex Logic Designs

— Programmable Output Polarity

— 100% Functional Testability

— Glue Logic for 3.3V Systems

— DMA Control

— State Machine Control

— High Speed Graphics Processing

— Standard Logic Speed Upgrade

CELL TECHNOLOGY

(GAL22LV10C)

Advanced CMOS Technology

CMOS process, which combines CMOS with

) floating gate technology. High speed erase

CMOS

TECHNOLOGY

Functional Block Diagram

Pin Configuration

I/CLK

GAL22LV10

Low Voltage E

Top View

GAL22LV10

PLCC

Generic Array Logic™

PRESET

RESET

OLMC

CMOS PLD

I/O/Q

August 2006

I/O/Q

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