74LV123DB,118 NXP Semiconductors, 74LV123DB,118 Datasheet - Page 13

• Manufacturer Part Number: 74LV123DB,118
• Description: IC DUAL RETRIG MULTIVIB 16SSOP
• Manufacturer: NXP Semiconductors
• Series: 74LVr

Specifications of 74LV123DB,118

• Logic Type: Monostable
• Package / Case: 16-SSOP
• Independent Circuits: 2
• Schmitt Trigger Input: Yes
• Propagation Delay: 14ns
• Current - Output High, Low: 12mA, 12mA
• Voltage - Supply: 1 V ~ 5.5 V
• Operating Temperature: -40°C ~ 125°C
• Mounting Type: Surface Mount
• Elements Per Chip: 2
• Logic Family: LV
• Propagation Delay Time: 120 ns, 40 ns
• High Level Output Current: - 12 mA
• Low Level Output Current: 12 mA
• Supply Voltage (max): 5.5 V
• Supply Voltage (min): 1 V
• Maximum Operating Temperature: + 125 C
• Minimum Operating Temperature: - 40 C
• Mounting Style: SMD/SMT
• Operating Supply Voltage: 3.3 V
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant, Lead free / RoHS Compliant
• Other names: 74LV123DB-T; 74LV123DB-T; 935210260118

NXP Semiconductors
12. Application information
74LV123_5
Product data sheet
12.1.1 Basic timing
12.1 Timing components
Table 9.
The basic output pulse width is essentially determined by the values of the external timing
components R
If C
The inherent test jig and pin capacitance at pin 15 and pin 7 (nREXT/CEXT) is
approximately 7 pF.
Supply voltage
V
< 2.7 V
2.7 V to 3.6 V
Fig 9. Timing components connections
CC
t
R
C
K = constant: this is 0.45 for V
4.5 V
W
EXT
EXT
EXT
(1) For minimum noise generation it is recommended to ground pins 6 (2CEXT) and 14 (1CEXT)
= output pulse width in ns
> 10 nF, the following formula is valid: t
= external resistor in k
= external capacitor in pF
externally to pin 8 (GND).
Test data
EXT
and C
Rev. 05 — 8 November 2007
Input
V
V
2.7 V
V
I
CC
CC
EXT
nA
nB
.
Dual retriggerable monostable multivibrator with reset
1 (9)
2 (10)
CC
t
r
74LV123
, t
2.5 ns
2.5 ns
2.5 ns
= 5.0 V and 0.48 for V
f
GND
8
(1)
nCEXT
14 (6)
W
C EXT
Load
C
50 pF
50 pF
50 pF
L
= K
3 (11)
nRD
15 (7)
001aae525
nREXT/CEXT
R
R EXT
13 (5)
4 (12)
EXT
CC
= 2.0 V (see
V
CC
C
R
1 k
1 k
1 k
nQ
nQ
EXT
L
(typ.) where:
© NXP B.V. 2007. All rights reserved.
74LV123
Figure
Test
t
t
t
PHL
PHL
PHL
10)
, t
, t
, t
13 of 23
PLH
PLH
PLH