74VCX162839MTDX Fairchild Semiconductor, 74VCX162839MTDX Datasheet - Page 2

• Manufacturer Part Number: 74VCX162839MTDX
• Description: IC REGISTER BUFFER 56-TSSOP
• Manufacturer: Fairchild Semiconductor
• Series: 74VCXr

Specifications of 74VCX162839MTDX

• Logic Type: Register, Multiplexed
• Output Type: Standard
• Number Of Elements: 1
• Number Of Bits Per Element: 20
• Function: Universal
• Voltage - Supply: 1.65 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 56-TSSOP
• Logic Family: VCX
• Logical Function: Register/Driver
• Number Of Elements: 1
• Number Of Bits: 20
• Number Of Inputs: 20
• Number Of Outputs: 20
• High Level Output Current: -12mA
• Low Level Output Current: 12mA
• Package Type: TSSOP
• Propagation Delay Time: 9.8ns
• Operating Supply Voltage (typ): 1.8/2.5/3.3V
• Operating Supply Voltage (max): 3.6V
• Operating Supply Voltage (min): 1.65V
• Clock-edge Trigger Type: Positive-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 250(Min)MHz
• Mounting: Surface Mount
• Pin Count: 56
• Operating Temp Range: -40C to 85C
• Operating Temperature Classification: Industrial
• Quiescent Current: 20uA
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant

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Connection Diagram
Logic Diagram
2
Truth Table
H
L
X
Z
Functional Description
The 74VCX162839 consists of twenty selectable non-
inverting buffers or registers with word wide modes. Mode
functionality is selected through operation of the CLK and
REGE pin as shown by the truth table. When REGE is held
at a logic HIGH the device operates as a 20-bit register.
Data is transferred from I
CLK input. When the REGE pin is held at a logic LOW the
device operates in a flow through mode and data propa-
gates directly from the I
be 3-stated by holding the OE pin at a logic HIGH.
Logic LOW
High Impedance
LOW-to-HIGH Clock Transition
Logic HIGH
Don’t Care, but not floating
CLK
X
X
X
REGE
H
H
X
L
L
Inputs
n
to the O
n
to O
I
H
H
X
L
L
n
n
n
on the rising edge of the
outputs. All outputs can
OE
H
L
L
L
L
Outputs
O
H
H
Z
L
L
n