HDSP-3400 Agilent(Hewlett-Packard), HDSP-3400 Datasheet
HDSP-3400
Related parts for HDSP-3400
HDSP-3400 Summary of contents
Page 1
HDM8513A Users Manual DVB/DSS Compliant Receiver Nov. 2000 Revision 1.0 Electronics Industries Co., Ltd. 1 ...
Page 2
Direct Broadcast Satellite (DBS) has been one of the most successful new product introductions in the history of consumer electronics. This product represents the first application of digital video compression for broadcast television. Originally intended to provide cable quality television ...
Page 3
Hyundai Electronics Ind. Co., Ltd reserves the right to make changes to its products or specifications to improve performance, reliability, or manufacturability. Information furnished by Hyundai Electronics Ind. Co., Ltd is believed to be accurate and reliable. However, no responsibility ...
Page 4
TABLE OF CONTENTS 1. INTRODUCTION TO THE HDM8513A................................................................................................................6 1 ..................................................................................................................................7 EATURES AND ENEFITS 2. HARDWARE SPECIFICATION..............................................................................................................................8 3. TECHNICAL OVERVIEW..................................................................................................................................... 18 3 UAL HANNEL NALOG TO 3 ARIABLE ATE EMODULATOR 3 ...
Page 5
IGURE OTOROLA EAD IMING IGURE OTOROLA RITE IMING IGURE UTPUT IMING IAGRAM FOR F 10 IGURE UTPUT IMING IAGRAM FOR F 11: ...
Page 6
Introduction to the HDM8513A The HDM8513A digital demodulator for direct broadcast satellite receivers is a single chip solution fully compliant with the European Telecommunications Standards Institute (ETSI) specification ETS 300 421. This chip integrates an A/D converter, a variable ...
Page 7
Features and Benefits * Fully DVB&DSS compliant * Dual 6bit A/D converters * Continuously variable symbol rate from 1Msps to 55Msps (75MHz clock) * Internal digital root raised cosine filter * Less than 0.5 dB implementation loss * Frequency ...
Page 8
Hardware Specification Table 1: Absolute Maximum Ratings Rating Ambient Temperature under Bias Storage Temperature Ambient Humidity under Bias Thermal Resistance(J a) Junction Temperature Voltage on Any Pin VDD, IOVDD Package Material Table 2: DC Characteristics Symbol Parameter I Dynamic ...
Page 9
Table 3: Demodulator Specifications Parameter Sampling Clock Frequency Analog Input Full Scale Range Symbol Rate Viterbi Data Rate Reed Solomon Data Rate Implementation Loss Symbol Rate Resolution Carrier Frequency Resolution Acquisition Sweep Range Table 4: AC Characteristics Symbol Parameter t ...
Page 10
Table 5: Intel 80C88A Read Cycle Timing Parameters (Busmode = 1) Symbol t su1 Input Address and /CE Setup before /RE Inactive t h1 Input Address and /CE Hold after /RE Inactive t pw1 /RE Low Duration t d1 Delay ...
Page 11
Table 6: Intel 80C88A Write Cycle Timing Parameters (Busmode = 1) Symbol t su1 Input Data Setup before /WE Inactive t h1 Input Address, Data and /CE Hold after /WE Inactive t pw1 /WE Low Duration t d1 Delay from ...
Page 12
Table 7: Intel 8051 Read Cycle Timing Parameters (Busmode = 1) Symbol t su1 Input Address Setup before /CE Active t h1 Input Address and /CE Hold after /RE Inactive t pw1 /RE Active Duration t pd1 Delay from /RE ...
Page 13
Table 8: Intel 8051 Write Cycle Timing Parameters (Busmode = 1) Symbol t su1 Input Address and Data Setup before /WE Active t h1 Input Address and Data Hold after /WE Inactive t pw1 /WE Active Duration t su2 /CE ...
Page 14
Table 9: Motorola Read Cycle Timing Parameters (Busmode =0) Symbol t su1 Setup Time of R/W with respect to /CE Active t su2 Address Setup with respect to /DS Active t d1 Delay from DTACK Active to Data Valid t ...
Page 15
Table 10: Motorola Write Cycle Timing Parameters (Busmode =0) Symbol t su1 Data Setup to /DS Active t su2 R/W Setup to /CS and Address t d1 /DS Delay from R DTACK Delay from /DS Active t d3 ...
Page 16
Table 11: Output Timing Symbol t su Output Data Setup before DATA_CLK and DATA_STB t hd Output Data Hold after DATA_CLK and DATA_STB DATA_CLK DATA_STB FRAME_SYNC DATA_VALID n-3 n-2 n-1 n DATA IGURE UTPUT DATA_CLK DATA_STB FRAME_SYNC ...
Page 17
DATA_CLK DATA_STB FRAME_SYNC DATA_VALID DATA n-3 n-2 n 11: O IGURE UTPUT DATA_CLK DATA_STB FRAME_SYNC DATA [ 8n-8 8n-7 8n-6 F 12: O IGURE UTPUT DATA_CLK FRAME_SYNC DATA_STB DATA [0] 8n 8n-7 8n-6 ...
Page 18
Technical Overview 3.1 Dual Channel Analog to Digital Converter The block diagram shown below illustrates internal configuration of the Dual Channel ADC. Baseband signals, in-phase(I) and quadrature phase(Q), which are generated by down converters, are applied to the dual ...
Page 19
VTOP 6-bit ADC AIN_I REF_I CLOCK 6-bit ADC AIN_Q REF_Q VBOT F 14: ADC B IGURE 6 DI Ref. Voltage Gen LOCK IAGRAM 19 ...
Page 20
Variable Rate Demodulator The block diagram illustrates the overall configuration of the variable rate QPSK demodulator. Baseband in-phase (I) and quadrature (Q) inputs are applied to the demodulator at a fixed sampling rate. These digital samples are produced by ...
Page 21
An analog wideband AGC is also employed to insure that the analog signal applied to the A/D converters is properly scaled. Both the symbol timing and carrier tracking loops are implemented digitally, which eliminates the need for ...
Page 22
Noise Measurement Circuit When the DBS system is being installed in any place, the most difficult part of the installation is accurate pointing of the antenna toward the satellite. Inaccurate pointing results in loss of margin and greater potential ...
Page 23
F 17 IGURE OISE CCUMULATOR AS A FUNCTION OF SNR T AND IME 23 ...
Page 24
Viterbi Decoder The Viterbi decoder accepts 3 bit soft decision samples of the in-phase (I) and quadrature (Q) components of the received signal. Once QPSK lock has been achieved, the decoder searches for the correct code rate, starting with ...
Page 25
Autonomous Acquisition The HDM8513A provides several features to permit signal acquistion with minimal interaction with the host microcontroller. The host microcontroller must configure the HDM8513A for a specific symbol rate, carrier frequency, carrier sweep conditions, and tracking loop bandwidth. ...
Page 26
The table below illustrates a typical acquisition timing. For this example, the symbol rate is one half of the clock rate. The code rate is set to 5/6, which requires 13 trial and errors before node sync is achieved. The ...
Page 27
Reed Solomon Decoder The serial output from the Viterbi is provided to the Word Sync circuits which searches for the eight bit frame sync word which occurs every 204 bytes. By detecting the polarity of the sync word, this ...
Page 28
Viterbi 8 Data Word Sync. Viterbi Clock Word Clock Frame Clock F 28 Deinterleaver Memory 8 Reed Deinterleaver Solomon Memory Decoder Control 19 IGURE EED OLOMON ECODER Error Flag 8 8 Data Descrambler Out Sync. Data Clock ...
Page 29
Clock Generation PLL An integrated VCO is locked to MxN times a reference frequency provided by a external clock. F Ref Reference ext_clk Divider 1 IGURE This programmable PLL consists of a PLL analog core, a ...
Page 30
DBS Receiver The HDM8513A DVB Demodulator including a dual A/D converter and the MPEG-2 decoder provide the core digital processing technology for a DBS receiver conforming with the DVB standard MHz Loo p Filter I L-B and ...
Page 31
Mechanical Specifications 4.1 100 Pin Quad Flat Pack 4.1.1 Pin Assignment 1 DATA_CLK 26 2 FRAME_ERROR 27 3 FRAME_SYNC 28 4 VDD 29 5 VSS 30 6 LNB_TONE 31 7 SIGMADELTA 32 8 SYMBOL_CLOCK 33 9 WB_AGC 34 10 ...
Page 32
Package Dimensions 80 81 17.880 17.908 14.100 13.900 100 1 0.380 0.220 0.500 0.250 F IGURE 32 23.340 23.090 20.100 19.900 HDM8513A DVB Demodulator 0.650 Typ. All Dimensions in mm 3.350 3.000 0.230 0.7 0.130 0.950 0.650 1.950 Typ. ...
Page 33
Pin Thin Quad Flat Pack 4.2.1 Pin Assignment 1 FRAME_ERROR 17 2 FRAME_SYNC 18 3 LNB_SYNC 19 4 WB_AGC 20 5 IOVDD 21 6 IOVSS 22 7 TEST13 23 8 TEST12 24 9 VDD 25 10 VSS 26 ...
Page 34
Package Dimensions 48 49 HDM8513AT 0.17 Min. 64 0.27 Max. 1 0.95 Min. 1.00 Typ. 1.05 Max. 0.15 Max. F IGURE 34 12.00 10. 0.50 All Dimensions Min. 0.08R Min. 23 ECHANICAL ...
Page 35
Recommended Analog Pin Connection 0.1uF I Down AIN_I Converter AIN_Q Q 0.1uF HDM8513A F 4.4 Recommended Clock Generation Circuit F 25: CLOCK GENERATION CIRCUIT IGURE 1.2uH VDD VDD 0.1uF VTO VBO REF_Q REF_I 0.1uF VSS VSS 0.1uF 0.1uF AGND ...
Page 36
Signal Description 5.1 Inputs XTAL1 XTAL1 can be configured either for sampling clock input or PLL reference clock input . The sampling clock rate must be a minimum of 1.33 times the symbol rate of the signal to be ...
Page 37
DATA_CLK The DATA_CLK is used to latch data and control signal of transport stream. The data and control signals can be programmed to be latched either at positive or negative edge of DATA_CLK. This signal is used in conjunction with ...
Page 38
VB_CLOCK The positive edge of this signal indicates that VB_DATA is valid. SIGMADELTA This is an one bit Sigma Delta D/A converter which has 8 bits of resolution. This output must be filtered with an analog low pass filter off ...
Page 39
Monitor and Control Interface Three different modes are supported for the monitor and control interface. Two of the modes are 8 bit parallel interfaces, one which supports Intel microcontrollers and the other intended for Motorola microcontrollers. The third mode ...
Page 40
I2C Mode The HDM8513A utilizes the subaddress technique when the I2C mode is employed. In all cases, the HDM8513A behaves as the slave device (transmitter or receiver), whilst the host behaves as the master device. The seven bit slave ...
Page 41
HDM8513A slave address, this time with the read/not write bit set to one (read). This will be acknowledged by the HDM8513A, which then assumes the role of slave transmitter and transmits the requested byte. This byte should be ...
Page 42
Register Definitions 6.1 Write Registers ADDRESS (Hex) 00, 01, 02 Symbol Timing Frequency The 20 bit straight binary number in this field establishes the symbol timing frequency utilized within the demodulator. Bit 7 of address 00 is the MSB ...
Page 43
Carrier Loop Filter Control This field establishes the K1 and K2 gain values for the second order loop filter of the carrier tracking loop. Bits 0,1,2 and 3 determine the straight- through gain, and bits 4,5, 6 and ...
Page 44
Narrow Band AGC initial value The six most significant bits of this field establish the initial gain of the AGC. High numbers correspond to low gain associated with low symbol rates. If the narrowband AGC function is enabled, this ...
Page 45
Control Parameters Bit 0. Binary/Two’s Complement When this bit is a zero, the system expects the six bit modulation input samples in two’s complement format, otherwise the input should be in offset binary format. Bit 1. Spectrum Invert When ...
Page 46
Reset Functions Bit 0. Symbol Timing Frequency Accumulator When this bit is set to zero, the frequency accumulator in the symbol tracking loop is cleared to zero. This bit must be set to one in normal tracking operation to ...
Page 47
Wideband AGC Control Bit 0. Wideband AGC Mode When this bit is set to one (Mode 0), the WB AGC output must be filtered with an external integrating analog filter to implement a first order feedback loop. When this ...
Page 48
Test Set-up The eight bit data written to this location defines the data presented on the 16 bit test bus. For configurations where the data is updated once per symbol period, the data changes at the rising edge of ...
Page 49
Bit 4. This bit should be fixed to zero Bit 5. Regulated Data Clock Enables/Disables the data and data clock regulator. When this bit is set to 1, data output and data clock are regulated by FIFO operation. When this ...
Page 50
Viterbi Byte-Sync control Once the viterbi lock(VB_NODESYNC) is achieved, the Viterbi decoder tries to find the byte-sync. This 8-bit register is used to set “unlock- threshold” for the byte-sync. Large number means it needs more bad- data to get ...
Page 51
Control Parameters for Viterbi and RS Decoders Bit 0. Parallel or Serial Output Controls the transport stream output of the 8513A to serial or parallel mode. “0” (default) means the 8513A MPEG output is parallel. “1” means the 8513A ...
Page 52
Rate 2/3 Threshold Select This seven bit parameter defines the threshold used in the node synchronization process. For rate 2/3, the nominal value is 30 (1EH). 1B Rate 3/4 Threshold Select This seven bit parameter defines the threshold used ...
Page 53
Clock Generation PLL Control An integrated VCO is locked to MxN times a reference frequency provided by a external clock Bits [4:0]. N Divider ratio It defines a feedback divider with a divider ratio N. The dafault is 15 ...
Page 54
Example for determination of internal clock Desired internal clock: External clock supplied: N divider ratio range: 1 – 31 (integer) M divider ratio range (integer) Calculation is as follows: <Example 1> Desired internal clock: 60MHz External clock ...
Page 55
Read Registers ADDRESS (Hex) 00 Narrowband AGC Accumulator The current value of the six bit AGC accumulator may be read from this location. 01, 02, 03 Symbol Timing Frequency Accumulator The current value of the 20 frequency accumulator in ...
Page 56
In-Phase The eight bit output of the In-phase baseband filter is available at this location. This data is updated once per symbol. 0C Quadrature The eight bit output of the quadrature baseband filter is available at this location. This ...
Page 57
FEC Lock Bit 0. Viterbi Node Sync When this bit is set to one, the Viterbi decoder has successfully established node synchronization. Bit 1. Frame Sync When this bit is set to one, the FEC chip has successfully established ...
Page 58
Appendix ...
Page 59
A1. Loop Filter Programming Application Note To illustrate that the symbol timing recovery loop and the carrier phase recovery loop are both programmable, several simulations were performed with different loop parameter conditions. These simulations were performed with a symbol rate ...
Page 60
Figure A2 illustrates the transient response of the carrier tracking loop with the same loop bandwidth settings at high signal-to-noise ratio. The phase step for this test corresponds to 45 degrees. The actual bandwidth of the carrier loop is greater ...
Page 61
F A3 IGURE ARRIER HASE ECOVERY RANSIENT ESPONSE WITH OW SNR 61 ...
Page 62
A2. False Lock Escape Application Note A QPSK signal will have inherent false lock states at frequency offsets n/4 of the symbol rate. Most DBS signals which have symbol rates of 20M symbols-per-second or higher will ...
Page 63
A3. Performance with Interference. In order to evaluate the filter employed within the HDM8513A with respect to attenuating out-of- band interference, a test was performed utilizing the COSSAP simulator. The desired signal, at zero frequency, was configured to utilize 16 ...
Page 64
F A4: A IGURE DJACENT HANNEL NTERFERENCE 1.35 S PACING ...
Page 65
F A5: P IGURE ERFORMANCE WITH INTERFERER AT DIFFERENT CARRIER SPACINGS 65 ...
Page 66
F A6: P IGURE 66 + ERFORMANCE WITH D NTERFERER ...
Page 67
A4. Nyquist Criteria Considerations The HDM8513A is clocked at 60MHz, yet processes signals with symbol rates as high as 45M symbols-per-second. At first thought, this might appear to be violating the Nyquist criteria which states that the sampling rate must ...