AK4129 AKM [Asahi Kasei Microsystems], AK4129 Datasheet
AK4129
Available stocks
Related parts for AK4129
AK4129 Summary of contents
Page 1
... The AK4129 is an 6ch digital sample rate converter (SRC). The input sample rate ranges from 8kHz to 216kHz. The output sample rate is from 8kHz to 216kHz. The AK4129 has an internal Oscillator and does not need any external master clocks. It contributes simplifying a system configuration. The AK4129 supports master mode and TDM data interface, enabling simultaneous input of asynchronous stereo data ...
Page 2
... Audio SDTI2 Input IBICK3 Serial ILRCK3 Audio SDTI3 IMCLK PDN PM1 PM2 uP I/F CAD0 SPB Figure 1. AK4129 Block Diagram (Synchronous mode INAS pin = “L”) BICK1 LRCK1 SDTI1 BICK2 LRCK2 SDTI2 BICK3 LRCK3 SDTI3 IMCLK PDN PM1 PM2 CAD0 SPB Figure 2. AK4129 Block Diagram (Asynchronous mode INAS pin = “H”) ...
Page 3
... Individual setting is available by DEM31-30, 21-20, 11-10 bits in serial control mode. Individual Setting Available Individual setting is available by IDIF32-30, 22-20, 12-10 bits in serial control mode. Available Parallel and Serial control modes are selected by the SPB pin. FSI:FSO Ratio Change Detect Detects over-current/voltage of the 1.8V outputs [AK4129] AK4129 2010/09 ...
Page 4
... XTO MCKO CAD0 TST1 SMSEMI TST2 SCL SDA SPB VD18 ILRCK2 [AK4129] AK4129 6ch mode AK4126 compatible (PM2/1 pin = “LL” AK4129 VD18 1uF Figure 4. AK4129 2010/09 ...
Page 5
... Ordering Guide −20 ∼ +85°C AK4129EQ −40 ∼ +85°C AK4129VQ AKD4129 Evaluation Board for AK4129 ■ Pin Layout MCKO 49 TST0 5 0 CAD0 VDD4 5 2 VSS5 5 3 TST1 5 4 SMSEM TST2 5 6 SCL 5 7 SDA SPB AVDD ...
Page 6
... Dither ON, “L” : Dither OFF Power-Down Mode Pin “H”: Power up, “L”: Power down reset and initializes the control register. The AK4129 should be reset once by bringing PDN pin = “L” upon power-up. Soft Mute Timer Select #0 Pin Soft Mute Timer Select #1 Pin ...
Page 7
... Parallel/Serial Control Mode Select Pin 59 SPB I MS1173-E-01 “H”: Semi-auto, “L”: Manual Mode 2 C Control Data In/Out put Pin, (when the SPB pin= “H”) “H”: Serial Control Mode, “L”: Parallel Control Mode - 7 - Function [AK4129] 2010/09 ...
Page 8
... The unused I/O pins should be processed appropriately as below. Classification Pin Name IBICK2, IMCLK, SDTI3, ILRCK3, IBICK3, SMUTE, DITHER, OMCLK/XTI, ILRCK2, SDA, SCL, Digital CAD0, TST0-6 UNLOCK, SDTO1-3, MCKO, XTO, TST7 MS1173-E-01 Function Setting These pins must be connected to VSS2-5. These pins must be open [AK4129] 2010/09 ...
Page 9
... ABSOLUTE MAXIMUM RATINGS Symbol AVDD DVDD1-4 IIN (Note 6) VIND AK4129EQ Ta AK4129VQ Ta Tstg Symbol AVDD DVDD1-4 AVDD - DVDD1 min max −0.3 4.2 −0.3 4.2 ±10 - −0.3 DVDD1-4+0.3 −20 85 −40 85 −65 150 min typ max 3.0 3.3 3.6 3.0 3.3 3.6 -0.3 0 +0.3 [AK4129] Units °C °C °C Units 2010/09 ...
Page 10
... FSI 8 216 FSO 8 216 −130 - −124 - −133 - −124 - - - -91 - 136 - 136 - 136 - 132 132 - - 140 1/6 6 min typ max 164 10 100 [AK4129] Units Bits kHz kHz - Units - μA 2010/09 ...
Page 11
... SA 121.4 SA 115.3 SA 116.9 SA 114.6 SA 100.2 SA 103.3 SA 102.0 SA 103.6 SA 103.3 SA 101.5 SA 73.2 (Note 15 [AK4129] typ max Units 0.4583FSI kHz 0.4167FSI kHz 0.3195FSI kHz 0.2852FSI kHz 0.2182FSI kHz 0.2177FSI kHz 0.1948FSI kHz 0.1458FSI kHz 0.1302FSI kHz 0.0917FSI kHz 0.0826FSI kHz 0.0583FSI kHz ...
Page 12
... Units - - V - 30%DVDD1 0 0.4 ±10 μA - typ max Units 24.576 MHz 36.864 MHz 27.648 MHz ...
Page 13
... FSO - - 1/8 FSO - [AK4129] kHz % kHz kHz kHz kHz kHz kHz % % kHz ns ns kHz ...
Page 14
... PDN Pulse Width Note 17. BICK rising edge must not occur at the same time as LRCK edge. Note 18. The AK4129 can be reset by bringing the PDN pin = “L”. Note 19. When OMCLK=512FSO. If the OMCLK=256FSO, OMCLK clock is though and output from the OBICK pin. When OMCLK = 384FSO, dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%] or (tCLKL)/(tCLKL+1/fCLK) x100 [%] ...
Page 15
... Note 20. Data must be held for sufficient time to bridge the 300 ns transition time of SCL. MS1173-E-01 Symbol min fSCL 1.3 tBUF tHD:STA 0.6 tLOW 1.3 tHIGH 0.6 tSU:STA 0.6 (Note 20) tHD:DAT 0 tSU:DAT 0 tSU:STO 0.6 tSP [AK4129] typ max - 400 - - - - - - - - 0 400 Units kHz μs μs μs μs μs μs μs μ ...
Page 16
... Figure 6. ILRCK1-3, IBICK1-3 Clock Timing - 16 - [AK4129] VIH VIL VIH VIL 50%DVDD VIH VIL Duty = tLRCH (or tLRCL) x FSI x 100 VIH VIL VIH VIL VIH VIL ...
Page 17
... Duty = tLRCH (or tLRCL) x FSO x 100 1/ fBCK tBICKH tBICKL dBCK = tBICKH(or tBICKL) x fBCK x 100 1/FSO tLRH 1/FSO tLRL 1/ fBCK tBICKH tBICKL dBCK = tBICKH(or tBICKL) x fBCK x 100 - 17 - [AK4129] VIH VIL VIH VIL VIH VIL VIH VIL 50%DVDD 50%DVDD 50%DVDD 50%DVDD 50%DVDD 2010/09 ...
Page 18
... Figure 9. Input PORT Audio Interface Timing (Stereo Slave mode and TDM256 Slave Mode) O LRCK tBLR O BICK tLRS SDTO Figure 10. Output PORT Audio Interface Timing (TDM256 Slave mode & Stereo Slave mode) MS1173-E-01 tLRB tSDS tSDH tLRB - 18 - [AK4129] VIH VIL VIH VIL VIH VIL VIH VIL VIH VIL tBSD 50% D VDD ...
Page 19
... Figure 11. Output PORT Audio Interface Timing (TDM256 Master mode & Stereo Master mode) PDN SDA tLOW tBUF SCL tHD:STA Stop Start MS1173-E-01 tPD Figure 12. Power Down Timing tR tHIGH tF tHD:DAT tSU:DAT tSU:STA Start 2 Figure 13 Bus Timing - 19 - [AK4129] 50%DVDD 50%DVDD tBSD 50%DVDD VIL VIH VIL tSP VIH VIL tSU:STO Stop 2010/09 ...
Page 20
... Asynchronous Inputs mode (INAS pin = “H”) does not support TDM mode. The AK4129 is not able to operate correctly because of SDTI1-3 data inputs are incorrect. TDM mode is must be OFF, when using the AK4129 in asynchronous inputs mode (INAS pin = “H”). The maximum input frequency of IBICK1-3 is 256FSI. ...
Page 21
... Lch Data Figure 15. Mode 1 Timing (20bit, LSB justified Don't Care 23 22 Lch Data Figure 16. Mode 2 Timing (24bit, MSB justified [AK4129] ILRCK IBICK IBICK1-3 1-3 1-3 Freq ≥ 32FSI ≥ 40FSI ≥ 48FSI ≥ 48FSI Input Input 32FSI ≥ ...
Page 22
... R2 32 IBICK 32 IBICK 32 IBICK 2 S, SDTI2-3: Don’t care Don't Care Rch Data Rch Data IBICK 32 IBICK IBICK 32 IBICK [AK4129 2010/09 ...
Page 23
... Slave (Bypass) Master (Bypass) Master (Bypass) Master (Bypass) Master (Bypass) Not used (Note Master (Bypass) Slave (Bypass) Master (Bypass) Slave (Bypass) Master (Bypass [AK4129] MCKO Output FSO 256FSO 8k∼108kHz 44.1~96kHz 384FSO 8k∼96kHz 29.4~64kHz 512FSO 22.05~48kHz 8k∼54kHz 768FSO 14.7~32kHz 8k∼48kHz OMCLK Input 8k∼ ...
Page 24
... The OLRCK pin and OBICK pin are input pins in slave mode. MS1173-E-01 460kΩ (typ) AK4129 Figure 21. X’tal Mode 11.2896 XTI 460kΩ (typ) XTO AK4129 Figure 22. External Clock (OMCLK) mode - 24 - [AK4129] The OMCLK/XTI pin is pulled down when the PDN pin= “L”. 12.288 24.576 60 15 2010/09 ...
Page 25
... SRC bypass mode, so that the data is not transferred correctly on SDTI1→SDTO1, SDTI2→SDTO2, and SDTI3→SDTO3 lines. In Asynchronous inputs mode (INAS pin = “H”), the AK4129 should be used in SRC mode. When the AK4129 is in slave mode, SDTI1-3 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode (Table 2) ...
Page 26
... When the AK4129 is in master mode, SDTI1-3 data are input by the ILRCK1 and IBICK1 clocks in SRC bypass mode (Table 2). The SDTI1-3 output data are output by the ILRCK1 and IBICK1 clocks in a format shown in 7. The ILRCK1 clock bypasses the SRC and it is output from the OLRCK pin. The IBICK1 clock bypasses the SRC and it is output from the OBICK pin ...
Page 27
... The SDTO1-3 is clocked out on the falling edge of OBICK. Select the audio interface format for output port when the PDN pin = “L”. If the AK4129 is in slave mode at bypass mode, IBICK1 and OBICK must be synchronized but the phase is not critical. ILRCK1 and OLRCK must be synchronized but the phase is not critical. The audio interface format of SDTO1, SDTO2 and SDTO3 are controlled together by ODIF1-0 pins, OBIT1-0 pins and TDM pin. Output ports become TDM mode when the TDM pin = “ ...
Page 28
... Rch Data [AK4129 ...
Page 29
... OBICK 32 OBICK 32 OBICK 2 S Compatible Timing at Slave Mode (SDTO2-3: “L” outputs 32OBICK OBICK 32 OBICK OBICK OBICK 32 OBICK [AK4129 2010/09 ...
Page 30
... Mode The AK4129 has AK4126 compatible 6-channel mode, AK4129 original 6-channel mode and 4-channel modes. When the PM2/1 pins are set to “L/L”, the AK4129 becomes AK4126 compatible 6-channel mode and six channels (SDTI1 SDTO1, SDTI2 SDTO2 and SDTI3 ...
Page 31
... Figure 32. Soft Mute Function (Manual Mode) 2. Semi-Auto Mode When power down of the AK4129 is released (PDN pin = “L” → “H”) with the SMSEMI pin= “H”, the AK4129 enters semi-auto mode. In this mode, soft mute is cancelled automatically 4410/FSO after a rising edge of PDN (100ms @FSO=44.1kHz). The soft mute is ON after releasing power down if the SMUTE pin = “ ...
Page 32
... Dither The AK4129 includes a dither circuit. The dither circuit adds a dither signal after the lowest bit of all the output data set by the OBIT1-0 pins when the DITHER pin = “H”, regardless of SRC and SRC bypass modes. If the output bit is 24bit length in SRC bypass mode, the output code does not change by the DITHER pin setting. ■ ...
Page 33
... AK4129 becomes reset state when over-current detection circuit or over-voltage detection circuit is operated. The AK4129 does not return to normal operation without a reset by the PDN pin when these detection circuits are worked. When over-current or over-voltage is detected, the PDN pin should be brought into “L” at once, and should be set to “ ...
Page 34
... I nt ernal Ci rc uit ILRCK1-4 Input wait Power-up Time “0” data “0” data “0” data Figure 35. System Reset [AK4129] Input Clocks Don’t care Input Data Don’t care Output Clocks Don’t care 21ms(max) Normal (2) ...
Page 35
... Internal Reset Function for Clock Change Clock change timing is shown in changing the clock, the AK4129 should be reset by the PDN pin in parallel control mode and it should be reset by the PDN pin or RSTN bit in serial control mode External clocks (Input port or Output port) ...
Page 36
... ILRCKx is input again. Note 38. When FSO=8kHz and FSO/FSI ratio is changed from 1/6 to 1/5.99 160.9ms when FSO=32kHz and FSO/fSI ratio is changed from 1/6 to 1/5.99. MS1173-E-01 and SRC data is output (Note 38) to output normal SRC data. Distorted data - 36 - [AK4129] (Note after “0.5/FSI+8/FSI(O)+156/FSO” 2010/09 38)to or ...
Page 37
... SRC Sampling Frequency Ratio Complete Flag UNLOCK pin In parallel control mode, if the AK4129 is set in SRC bypass mode by CM2-0 pins during the PDN pin = “L” and powered-up, the UNLOCK pin outputs “L” after the power-up time of the internal regulator (max. 1.4ms) from a rising edge “ ...
Page 38
... Data transfer All commands are preceded by a START condition. After the START condition, a slave address is sent. After the AK4129 recognizes the START condition, the device interfaced to the bus waits of the slave address to be transmitted over the SDA line ...
Page 39
... The AK4129 generates an acknowledge after each byte is received. In read mode, the slave, the AK4129 transmits eight bits of data, release the SDA line and monitor the line for an acknowledge acknowledge is detected and no STOP condition is generated by the master, the slave will continue transmitting data ...
Page 40
... The AK4129 is capable of more than one byte write operation by one sequence. After receipt of the third byte, the AK4129 generates an acknowledge, and awaits the next data again. The master can transmit more than one word instead of terminating the write cycle after the first data word is transferred. After the receipt of each data, the internal address counter is incremented by one, and the next data is taken into next address automatically. If the address exceeds 03H prior to generating a stop condition, the address counter will “ ...
Page 41
... After receipt of the slave address with R/W bit set to “1”, the AK4129 generates an acknowledge, transmits 1byte data which address is set by the internal address counter and increments the internal address counter the master does not generate an acknowledge but generate the stop condition, the AK4129 discontinues transmission ...
Page 42
... Reset 1: Reset Release (default) When this bit is set to “0”, some digital blocks of the AK4129 are powered-down. In this case SRC1-3 can not operate. Control register settings are not initialized because I²C serial control interface and control register blocks are not powered-down. Control register writings are available. The internal oscillator for the clocks, the regulator and the reference voltage generation circuit are not powered-down ...
Page 43
... IDIF21 IDIF20 RD R/W R/W R Table 2) Table 2) Table DEM21 DEM20 DEM11 R/W R/W R IDIF12 IDIF11 RD R/W R IDIF32 IDIF31 RD R/W R [AK4129] D0 DEM10 R IDIF10 R IDIF30 R/W 0 2010/09 ...
Page 44
... Top View XTO 48 OMCLK/XTI 47 FSO OLRCK 46 64FSO OBICK 45 C1 DVDD 44 VSS4 43 TST7 42 SDTO1 41 SDTO2 40 SDTO3 39 ODIF0 38 ODIF1 37 CM0 36 CM1 35 CM2 34 TDM [AK4129] DSP2 2010/09 ...
Page 45
... Top View XTO 48 XTI/OMCLK 47 FSO OLRCK 46 64FSO OBICK 45 C1 DVDD 44 VSS4 43 DSP5 SDTO4 42 SDTO1 41 SDTO2 40 SDTO3 39 ODIF0 38 ODIF1 37 CM0 36 CM1 35 CM2 34 TDM [AK4129] 2010/09 ...
Page 46
... The AK4129 requires careful attention to power supply and grounding arrangements. Alternatively if AVDD and DVDD1-4 are supplied separately, the power up sequence is not critical. VSS1-5 must be connected to the same ground plane. Decoupling capacitors should be as near to the AK4129 as possible, with the small value ceramic capacitor being the nearest. ...
Page 47
... Digital Filter Response Example Table 14 shows the examples of digital filter response performed by the AK4129. Ratio FSO/FSI [kHz] 4.000 192/48.0 1.000 48.0/48.0 0.919 44.1/48.0 0.725 32.0/44.1 0.667 32.0/48.0 0.544 48.0/88.2 0.500 48.0/96.0 0.500 44.1/88.2 0.459 44.1/96.0 0.363 32.0/88.2 0.333 32.0/96.0 0.250 48.0/192.0 0.250 44.1/176.4 0.230 44.1/192.0 0.167 32.0/192.0 0.181 32.0/176.4 0.167 8/48.0 0.181 8/44 ...
Page 48
... LQFP(Unit: mm 0.5 0.10 ■ Material & Lead finish Package molding compound: Lead frame material: Lead frame surface treatment: MS1173-E-01 PACKAGE 12.0 Max 1.85 10.0 1. 0.2±0.1 0.10 M 0°~10° 0.50±0.25 Epoxy Cu Solder (Pb free) plate - 48 - [AK4129] 0.00~0.25 0.09~0.25 2010/09 ...
Page 49
... MS1173-E-01 MARKING (AK4129EQ) AKM AK4129EQ XXXXXXX 1 XXXXXXX: Date code identifier MARKING (AK4129VQ) AKM AK4129VQ XXXXXXX 1 XXXXXXX: Date code identifier - 49 - [AK4129] 2010/09 ...
Page 50
... MHz” → “min. 59.4MHz” Error Correction 45 Figure 49 was changed. Specification 48 PACKAGE Change The package dimensions were changed. IMPORTANT NOTICE , and AKM assumes no responsibility for such use, except for the use Note2 [AK4129] in any safety, life support, or Note1) 2010/09 ...