AK4129 AKM [Asahi Kasei Microsystems], AK4129 Datasheet - Page 14

• Manufacturer Part Number: AK4129
• Description: 6ch 216kHz / 24-Bit Asynchronous SRC
• Manufacturer: AKM [Asahi Kasei Microsystems]

Reset Timing
Note 17. BICK rising edge must not occur at the same time as LRCK edge.
Note 18. The AK4129 can be reset by bringing the PDN pin = “L”.
Note 19. When OMCLK=512FSO. If the OMCLK=256FSO, OMCLK clock is though and output from the OBICK pin.
MS1173-E-01
Output PORT (TDM256 slave mode)
OBICK Period
OBICK Pulse Width Low
OLRCK Edge to OBICK “↑”
OBICK “↑” to OLRCK Edge
OBICK “↓” to SDTO1
Output PORT (Stereo Master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO1-3
Output PORT (TDM256 master mode)
OBICK Frequency
OBICK Duty
OBICK “↓” to OLRCK Edge
OBICK “↓” to SDTO1
PDN Pulse Width
When OMCLK = 384FSO, dBCK= (tCLKH)/(tCLKH+1/fCLK) x100 [%] or (tCLKL)/(tCLKL+1/fCLK) x100
[%]. When OMCLK=768FSO, dBCK= (1/fCLK)/(3/fCLK) x100 [%].
Pulse Width High
OMCLK=384FSO
OMCLK=768FSO
OMCLK pin
OBICK pin Ouput
(TDM256
OBICK pin Output
(TDM256
OMCLK pin
Master mode)
Master mode)
1/fCLK
1/fCLK
tCLKH
tCLKH
1/fCLK
3/fCLK
tCLKL
1/fCLK
1/fCLK
(Note
(Note
(Note
1/fCLK
18)
17)
17)
tCLKL
tCLKL
tBCKH
tMBLR
tBCKL
fBCK
dBCK
tMBLR
tBSD
dBCK
fBCK
- 14 -
tBCK
tLRB
tBLR
tBSD
tBSD
tPD
3/fCLK
1/fCLK
1/fCLK
−20
−20
−10
−20
150
81
32
32
20
20
-
-
50(Note
256 FSO
64 FSO
50
-
19)
20
20
20
10
20
-
-
[AK4129]
2010/09
Hz
Hz
ns
ns
ns
ns
ns
ns
%
ns
ns
%
ns
ns
ns