TXC-02050CIPL ETC1 [List of Unclassifed Manufacturers], TXC-02050CIPL Datasheet - Page 7

• Manufacturer Part Number: TXC-02050CIPL
• Description: MRT Device 6-,8-,34-Mbit Line Interface TXC-0250C
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

Alarm Signal Outputs
Symbol
Symbol
LQLTY
TP/TD
TXLOC
CLKO
CLKO
CLKI
TN
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Pin No.
Pin No.
14
15
38
40
41
2
5
I/O/P
I/O/P
O
O
O
O
I
I
I
CMOS8mA
CMOS8mA
(Tristate)
(Tristate)
TTL2mA
TTL2mA
Type
Type
TTLr
TTL
TTL
DATA SHEET
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Clock Out Inverted: Receive inverted clock output.
Positive and negative rail receive data is clocked out on
the rising edge. When PNENB is high or RXDIS is low,
this pin is forced to a high impedance state (disabled).
Clock Out: Receive clock output. Receive positive and
negative rail and NRZ data is clocked out on the falling
edge. When RXDIS is low, this pin is forced to a high
impedance state (disabled).
Clock In: Transmit clock input for P and N rail and NRZ
data. Transmit data is clocked into the MRT on the rising
edge. This clock must have a frequency accuracy of
for the 6312/8448 kbit/s operation (ref: ITU-T recom-
mendation G.703). The duty cycle requirement for this
clock signal is (50
threshold level.
Transmit Positive/Transmit Data: When PNENB is
low, the HDB3 codec is bypassed and transmit P-rail
(TP) data is applied to this pin. When PNENB is high,
NRZ transmit data (TD) is applied.
Transmit Negative: When PNENB is low, the HDB3
codec is bypassed and transmit N-Rail (TN) is applied to
this pin. When PNENB is high, this input is disabled.
Transmit Loss Of Clock: Active low output. A transmit
loss of clock alarm occurs when the transmit clock input
(CLKI) is stuck high or low for about 500 clock cycles.
Recovery occurs on the first input clock transition. DCK
is required for proper operation.
Line Quality: This signal represents an estimate of the
line quality which is determined by counting coding vio-
lations for 34 (8) Mbit/s operation. If the line error rate
exceeds a 10
val, LQLTY goes active high. LQLTY is active low when
coding violations do not exceed the 10
10 (40) second interval. The output on this pin is only
valid when the appropriate clock signal is applied to
BERCK. It should be disregarded in the P and N mode
of operation or in 6 Mbit/s operation.
20 ppm for the 34368 kbit/s operation and 30 ppm
-6
threshold during a 10 (40) second inter-
Name/Function
Name/Function
5) %, measured at the 1.4V TTL
-6
TXC-02050C
threshold in a
TXC-02050C-MB
Ed. 1, May 2002
MRT