TXC-02050CIPL ETC1 [List of Unclassifed Manufacturers], TXC-02050CIPL Datasheet - Page 8

• Manufacturer Part Number: TXC-02050CIPL
• Description: MRT Device 6-,8-,34-Mbit Line Interface TXC-0250C
• Manufacturer: ETC1 [List of Unclassifed Manufacturers]

MRT Control Leads
Symbol
Symbol
RXLOS
BERCK
PNENB
RXDIS
RXAIS
DCK
CV
Proprietary TranSwitch Corporation Information for use Solely by its Customers
Pin No.
Pin No.
19
20
21
3
4
8
9
I/O/P
I/O/P
O
O
I
I
I
I
I
TTL2mA
TTL2mA
CMOSr
CMOSr
CMOSr
Type
Type
TTLr
TTL
DATA SHEET
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Coding Violation: Active high output. A coding violation
pulse occurs when an HDB3 coding violation is detected
in the received line data input. A coding violation is not
part of the HDB3 zero-substitution code. A coding viola-
tion occurs because of noise or other impairments
affecting the line signal. The output of this pin should be
disregarded in the P and N mode.
Receive Loss Of Signal: Active low output. A receive
loss of signal occurs when the input data is zero for
40-50 s. Recovery occurs when the receive signal
returns.
Receive Alarm Indication Signal: When RXAIS is low,
the MRT generates AIS (all ones signal) for the terminal
side receive output data. The line side receive data path
is disabled. The reference clock (DCK) provides the
clock source required for generating AIS.
Bit Error Rate Clock: This clock establishes the time
base for estimating the coding violation error rate. For
34 Mbit/s operation the clock frequency must be 6 kHz,
and for 8 Mbit/s operation the clock frequency must be
1.5 kHz. This pin should be left open for P and N mode
operation.
P And N Enable: When PNENB is low, the P and N rail
interface is enabled, and the HDB3 codec is bypassed.
When PNENB is high, the terminal side I/O data is NRZ
and the HDB3 codec is enabled. This pin must be held
low for 6 Mbit/s operation.
Reference Clock: Operating frequency reference clock.
For receive signal clock recovery,
accuracy is adequate. If the transmit and receive AIS
features are used, the frequency accuracy must be 20
ppm for 34368 kbit/s and 30 ppm for 8448 and 6312
kbit/s operation. The duty cycle requirement for this
clock signal is (50 5) % as measured at the 1.4V TTL
threshold level.
Receive Disable: When RXDIS is low, the receive side
of the MRT is disabled and the RN, RP/RD, CLKO and
CLKO output leads are forced to a high impedance
state.
Name/Function
Name/Function
200 ppm frequency
TXC-02050C
TXC-02050C-MB
Ed. 1, May 2002
MRT