L-FW323-06-DB AGERE [Agere Systems], L-FW323-06-DB Datasheet - Page 21

• Manufacturer Part Number: L-FW323-06-DB
• Description: PCI PHY/Link Open Host Controller Interface
• Manufacturer: AGERE [Agere Systems]

Data Sheet, Rev. 1
December 2005
Pin Information
Table 1. Pin Descriptions (continued)
* Active-low signals within this document are indicated by an N following the symbol names.
Note: For those applications when one or more FW323 ports are not wired to a connector, those unused ports may be left unconnected without
Agere Systems Inc.
121
122
123
124
125
126
127
128
Pin
normal termination. When a port does not have a cable connected, internal connect-detect circuitry will keep the port in a disconnected
state.
VAUX_PRESENT
RESETN
Symbol*
PTEST
SM
XO
SE
NU
XI
(continued)
Analog I/O
Type
—
I
I
I
I
I
Crystal Oscillator. XI and XO connect to a 24.576 MHz parallel
resonant fundamental mode crystal. Although when a 24.576 MHz
clock source is used, it can be connected to XI with XO left uncon-
nected. The optimum values for the external shunt capacitors are
dependent on the specifications of the crystal used. It is necessary to
add an external series resistor to the XO pin. The value of the resistor
is nominally 400 Ω. For more details, refer to the Crystal Selection
Considerations section in this data sheet. Note that it is very impor-
tant to place the crystal as close as possible to the XO and XI pins,
i.e., within 0.5 in./1.27 cm. For more important details regarding the
crystal, refer to the FW323/FW322 Hardware Implementation Design
Guideline Application Note.
Reset (Active-Low). When RESETN is asserted low (active), a 1394
bus reset condition is set on the active cable port and the FW323 is
reset to the reset start state. To guarantee that the PHY will reset,
this pin must be held low for at least 2 ms. An internal pull-up resistor,
connected to V
(0.1 µF) and resistor (510 kΩ), in parallel, are required to connect this
pin to ground. This circuitry will ensure that the capacitor will be
discharged when PHY power is removed. The input is a standard
logic buffer and can also be driven by an open-drain logic output
buffer. Do not leave this pin unconnected. This pin is also used with
the EEPROM interface. It is the powerup reset pin. This pin is
asserted low (active) to indicate a powerup reset. Refer to the FW322
06/FW323 06 EEPROM Interface and Start-up Behavior Application
Note sections titled Initiation of EEPROM Load and Initial Powerup.
Test. Used by Agere for device manufacturing testing. Tie to V
normal operation.
Test Mode Control. SM is used during Agere’s manufacturing test
and should be tied to V
Test Mode Control. SE is used during Agere’s manufacturing test
and should be tied to V
Not Usable. No external connections to this pin are allowed.
3.3 Vaux Present. An active-high input indicating whether the
FW323 is powered via an auxiliary power supply (e.g., PCI 3.3 Vaux).
An internal pull-down resistor connected to V
external pull-up is only required when the device is being powered by
an auxiliary power supply. Note that VAUX_PRESENT is not an
actual power supply pin to the device. Rather, this pin is an indicator
of whether the FW323 is powered via an auxiliary power supply
(VAUX_PRESENT = 1) or the regular PCI power supply
(VAUX_PRESENT = 0). This input is used by the FW323 to properly
support the D3cold power management functionality.
PCI PHY/Link Open Host Controller Interface
DD
, is provided, so only an external delay capacitor
SS
SS
for normal operation.
for normal operation.
Description
SS
is provided, so an
FW323 06 1394a
SS
for
21