IDT72V73260BB IDT, Integrated Device Technology Inc, IDT72V73260BB Datasheet - Page 8

• Manufacturer Part Number: IDT72V73260BB
• Description: IC DGTL SW 16384X16384 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V73260BB

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V73260BB

TABLE 5 — CONTROL REGISTER (CR) BITS
TABLE 6 — CONNECTION MEMORY BITS
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
15, 14 MOD1-0
13-9
Bit
8-0
11-10
MOD1 MOD0
BIT
8-7
3-0
15
14
13
12
SRS
Reset Value:
9
6
5
4
15
15
CAB8-0
(Source Channel Address Bits)
(Switching Mode Selection)
SAB4-0
(Source Stream Address Bits)
Name
NAME
SRS
(Software Reset)
OEI
(Output Enable Indication)
OEPOL
(Output Enable Polarity)
AOE
(All Output Enable)
Unused
MBP
(Memory Block Program) bit 14 to bit 15. When 0, this feature is disabled.
BPD1-0
(Block Programming
Data)
BPE
(Begin Block
Programming Enable)
OSB
(Output Stand By)
SFE
(Start Frame Evaluation)
Unused
OEI
14
14
OEPOL
SAB4
13
13
SAB3
AOE
0000
12
12
H
MOD1 MOD0
SAB2
Description
The binary value is the number of the data stream for the source of the connection.
The binary value is the number of the channel for the source of the connection.
A one will reset the device and have the same effect as the RESET pin. Must be zero for normal operation.
When 1, the TX16-31/Output Enable Indication0-15 pins will be Output Enable Indication 0-15 and reflect the active or high-impedance
state of their corresponding output data streams. When 0, this feature is disabled and these pins are used as output data streams
TX16-31.
When 1, a one on an Output Enable Indication pin denotes an active state on the output data stream; zero on an Output Enable Indication
pin denotes high-impedance state. When 0, a one on an Output Enable Indication pin denotes high-impedance and a zero denotes
an active state.
When 1, TX0-31 will behave as Output Enable Indication0-31 accordingly. These outputs will reflect the active or high-impedance
state of the corresponding output data streams (TX0-31) in another IDT72V73260 if programmed identically. When 0, the TSI operates
in the normal switch mode.
Must be zero for normal operation.
When 1, the Connection Memory block programming feature is ready for the programming of Connection Memory HIGH bits,
These bits carry the value to be loaded into the Connection Memory block whenever the memory block programming feature
is activated. After the Memory Block Program bit in the Control Register is set to 1 and the Block Programming Enable is set to 1,
the contents of the bits BPD1-0 are loaded into bit 15 and 14 of the Connection Memory. Bit 13 to bit 0 of the Connection Memory
are set to 0.
A zero to one transition of this bit enables the memory block programming function. The Block Programming Enable and BPD1-0 bits
in the Control Register have to be defined in the same write operation. Once the Block Programming Enable bit is set HIGH, the
device requires two frames to complete the block programming. After the programming function has finished, the Block Programming
Enable, Memory Block Program and BPD 1-0 bits will be reset to zero by the device to indicate the operation is complete.
When ODE = 0 and Output Stand By = 0, the output drivers of the transmit serial streams are in high-impedance mode. When
either ODE =1 or Output Stand By =1, the output serial streams drivers function normally.
A zero to one transition in this bit starts the Frame Evaluation procedure. When the Complete Frame Evaluation bit in the Frame Alignment
zero for at least one frame.
Must be zero for normal operation.
Register changes from zero to one, the evaluation procedure stops. To start another Frame Evaluation cycle, set this bit to
11
11
0
1
1
DESCRIPTION
0
0
SAB1
10
10
0
1
0
1
0
SAB0
MBP
9
9
Constant Delay mode
Processor mode
Output high-impedance
Variable Delay mode
CAB8
BPD1
8
8
MODE
CAB7
BPD0
7
7
8
CAB6
BPE
6
6
CAB5
OSB
5
5
CAB4
SFE
4
4
CAB3
3
3
0
INDUSTRIAL TEMPERATURE RANGE
CAB2
2
2
0
CAB1
1
1
0
CAB0
0
0
0