IDT72V73260BB IDT, Integrated Device Technology Inc, IDT72V73260BB Datasheet - Page 9

• Manufacturer Part Number: IDT72V73260BB
• Description: IC DGTL SW 16384X16384 144-BGA
• Manufacturer: IDT, Integrated Device Technology Inc
• Series: 72Vr
• Type: Multiplexerr

Specifications of IDT72V73260BB

• Circuit: 1 x 32:32
• Independent Circuits: 1
• Voltage Supply Source: Single Supply
• Voltage - Supply: 3 V ~ 3.6 V
• Operating Temperature: -40°C ~ 85°C
• Mounting Type: Surface Mount
• Package / Case: 144-BGA
• Lead Free Status / RoHS Status: Contains lead / RoHS non-compliant
• Current - Output High, Low: -
• Lead Free Status / RoHS Status: Not Compliant, Contains lead / RoHS non-compliant
• Other names: 72V73260BB

TABLE 7 — FRAME ALIGNMENT REGISTER (FAR) BITS
IDT72V73260 3.3V TIME SLOT INTERCHANGE
DIGITAL SWITCH 16,384 x 16,384
15-14
11-0
Bit
13
12
Reset Value:
15
0
Name
Unused
CFE (Complete
Frame Evaluation)
FD12
(Frame Delay Bit 12) C32i-LOW phase (FD12 = 0). This bit allows the measurement resolution to ½ C32i cycle. This bit is reset to zero when the Start Frame Evaluation
FD11-0
(Frame Delay Bits)
ST-BUS
Offset Value
Offset Value
GCI Frame
14
0
FE Input
FE Input
C32i
C32i

Frame
CFE
13
FD12
When Complete Frame Evaluation = 1, the Frame Evaluation is completed and bits FD12 to FD0 bits contains a valid frame alignment offset.
Description
Must be zero for normal operation
This bit is reset to zero, when Start Frame Evaluation bit in the Control Register is changed from 1 to 0.
The falling edge of Frame Evaluation (or rising edge for GCI mode) is sampled during the C32i-HIGH phase (FD12 = 1) or during the
bit of the Control Register changes from 1 to 0.
The binary value expressed in these bits refers to the measured input offset value. These bits are reset to zero when the Start Frame Evaluation
bit of the Control Register changes from 1 to 0. (FD11 – MSB, FD0 – LSB)
0000
12
H
.
FD11
11
0
0
FD10
Figure 1. Example for Frame Alignment Measurement
1
1
10
2
2
FD9
9
3
3
FD8
8
4
4
5
5
FD7
7
9
(FD[11:0] = 06
(FD12 = 0, sample at CLK LOW phase)
6
6
FD6
6
7
7
FD5
8
8
5
H
(FD[11:0] = 09
(FD12 = 1, sample at CLK HIGH phase)
)
9
9
FD4
4
10
10
FD3
H
11
3
11
)
INDUSTRIAL TEMPERATURE RANGE
12
12
FD2
2
13
13
FD1
1
14
14
5932 drw04
15
FD0
15
0
16