HI-3110 HOLTIC [Holt Integrated Circuits], HI-3110 Datasheet
HI-3110
Related parts for HI-3110
HI-3110 Summary of contents
Page 1
... TTCAN protocol). The HI-3111 is a digital only version of the HI-3110 (no transceiver). This version provides a “protocol only” solution for customers who wish to use an external transceiver and may be used in situations where the customer requires galvanic isolation between the bus and digital protocol logic ...
Page 2
... OSCILLATOR OSCOUT CLOCK DIV CLKOUT OUT (see ordering information) PRIMARY FUNCTIONS OF HI-3110 LOGIC BLOCKS SPI PROTOCOL BLOCK Handles data transfers between the host and the chip REGISTERS BLOCK Stores configuration data BIT TIMING BLOCK Sets the data strobe and bit period ...
Page 3
... VLOGIC POWER 3.3V supply voltage input. This supply is used to drive the host digital logic I/O. It can either be connected directly to VDD (+5V +3.3V supply. GND POWER Supply voltage ground. HI-3110 DESCRIPTION CS HOLT INTEGRATED CIRCUITS 3 INTERNAL PULL UP / DOWN 50K ohm pull-down is low. 50K ohm pull-up ...
Page 4
... FUNCTIONAL OVERVIEW The HI-3110 is the first single chip product to integrate both the CAN (Controller Area Network) protocol and analog interface transceiver on a single IC. The protocol conforms to CAN version 2.0B and is compliant with 1:2003(E) specification . The transceiver is compliant with ISO 11898-5 specification. Configuration options include an internal Loopback mode ...
Page 5
... Monitor mode is activated by programming the MODE<2:0> bits to <010> in the CTRL0 register. SLEEP MODE The HI-3110 can be placed in a low power sleep mode if there is no bus activity and the transmit FIFO is empty. In this mode, the internal oscillator and all analog circuitry (transceiver) are off, drawing typically less than 20 A ...
Page 6
... After the control field is the data field, which contains a data payload equal to the number of bytes specified by the DLC (see note above). HI-3110 The data field is followed by the 16-bit Cyclic Redundancy Check (CRC) field. This is used to check transmission errors by computing a 15-bit CRC sequence from the previous bit stream (SOF, arbitration field, control field and data field, excluding stuff bits) ...
Page 7
... Note 1): The HI-3110 will never initiate an overload frame unless reacting to one of the conditions in case 1) above. Note 2): Initiation of overload frames is prohibited by ARINC 825 since they increase the network loading. ...
Page 8
... Standard Data Frame HI-3110 SOF or Idle Bus Intermission Del ACK bit Slot ACK KEY. Del CRC SOF IDxx RTR IDE r0 DLCx CRC Del ACK Slot bit ACK Del EOF IFS DLC0 DLC3 r0 bit Reserved IDE RTR ID18 ID23 ID28 SOF Figure 2. Standard Frame Format. ...
Page 9
... Extended Data Frame HI-3110 SOF or Idle Bus Intermission Del ACK bit Slot ACK Del CRC KEY. SOF IDxx SRR IDE RTR r1 r0 DLCx CRC Del ACK Slot bit ACK Del EOF IFS DLC0 DLC3 r0 bits Reserved r1 RTR ID0 ID9 ID17 IDE ...
Page 10
... Remote Frame Figure 4. Remote Frame Format (Extended Identifier). HI-3110 SOF or Idle Bus Intermission Del ACK bit Slot ACK Del CRC DLC0 DLC3 r0 bits Reserved r1 RTR ID0 ID9 ID17 IDE SRR ID18 ID23 ID28 SOF HOLT INTEGRATED CIRCUITS 10 ...
Page 11
... Error Frame HI-3110 Intermission DLC0 DLC3 r0 bits Reserved r1 RTR ID0 ID9 ID17 IDE SRR ID18 ID23 ID28 SOF Figure 5. Error Frame Format. HOLT INTEGRATED CIRCUITS 11 ...
Page 12
... Overload Frame HI-3110 Intermission Illegal Dominant Bit in IFS Figure 6. Overload Frame Format HOLT INTEGRATED CIRCUITS 12 ...
Page 13
... TXCAN: Node 2 TXCAN: Node 3 CAN Bus differential signal (not to scale) HI-3110 Bitwise arbitration works by comparing each node’s transmitted data bit by bit. All nodes are synchronized by adjusting individual bit times as a function of bit time quanta (see section on bit timing). Synchronization takes place on recessive to dominant edges ...
Page 14
... Seg), phase buffer segment 1 (Phase Seg1) and phase buffer segment 2 (Phase Seg2). This is illustrated in figure 8. The HI-3110 fixes the Sync Seg at 1Tq. Prop Seg and Phase Seg1 are treated as one time segment, TSeg1, which is programmable from 2Tq to 16Tq. ...
Page 15
... The phase buffer segments are used to compensate for phase errors on the bus. Phase Seg1 can be lengthened or Phase Seg2 can be shortened duringthe re-synchronization bit period automatically by the HI-3110 so that the bit time can be adjusted to account for phase errors. The upper limit by which the lengthening ( or shortening) can occur is set by ...
Page 16
... REGISTERS This section describes the HI-3110 registers. All register bits are active high. Unless otherwise indicated, all registers are reset in software to the logic zero condition after Master Reset. For all registers, bit 7 is the most significant: REGISTER R/W CTRL0 R/W CTRL1 R/W BTR0 R/W BTR1 ...
Page 17
... When this bit is set, the HI-3110 will automatically wake up from Sleep Mode to Monitor Mode when it detects activity on the bus. 3 RESET R/W 0 Setting this bit causes HI-3110 reset to occur. The bit should then be cleared by writing a logic “0” following reset. A reset may also be performed by setting the MR pin or issuing the “MR” SPI command, 0x56. 2 BOR R/W 0 Bus-off Reset ...
Page 18
... Time-Triggered CAN standard (TTCAN). 4 FILTON R/W 0 Filter on enable. This bit is set to turn on the HI-3110 CAN ID filtering mechanism. The default after reset is FILTON = 0, meaning filtering is turned off and every valid CAN message is accepted into the receive FIFO. acceptance filters and masks. 3 OSCOFF ...
Page 19
... Note that one time quantum (Tq) is the single unit of time within a bit time (see Bit Timing section). Note: 5-0 BRP5:0 R/W 0 Baud Rate Prescaler bits <5:0>. The baud rate prescaler relates the system oscillator frequency, f described in the bit timing section. HI-3110 MSB SJW bits <1:0> ...
Page 20
... Prop Seg + Phase Seg1. Note: Not all combinations are valid, since Prop Seg + Phase Seg1 minimum number bit time shall be 8. Notes: this case, Tseg1 should be a minimum of 5Tq for Phase Seg2 (Tseg2) = 2Tq and SJW = 1Tq. HI-3110 ...
Page 21
... TEC > 255: Bus-off status. Bus-off flags, BUSOFF, set in ERR and STATF registers. The latter may be used to generate a hardware interrupt if BUSOFFIE bit is set in STATFE register. The HI-3110 will, after entering bus-off state, automatically recover to error active status without host intervention if the BOR bit is set in control register CTRL0 and 128 x 11 consecutive recessive bits are detected on the bus ...
Page 22
... Message Tag bits <1:0>. These bits will reflect the last two bits of the host assigned message tag of the last successful transmission. 1-0 TSTAT1 Transmission Status bits <1:0>. These bits reflect the transmission status. HI-3110 MSB 0000: No filter matches the received message. ...
Page 23
... Default Description 7 BUSOFF R 0 Bus-off status indicator. This bit is set when TEC > 255. Node is in bus off condition. The bit is reset by HI-3110 when a successful bus recovery sequence is detected (128 x 11 consecutive recessive bits). d the FILHIT3:0 bits will reflect this value. 6 TXERRP R 0 Transmit Error Passive status indicator ...
Page 24
... SPI Op-code 0xDE) The Interrupt Flag Register INTF bits will be set by HI-3110 when the corresponding related events described below occur. If individual bits in the Interrupt Enable Register INTE are set, the INT pin will be latched high when any of the corresponding INTF bits are set ...
Page 25
... SPI Op-code 0x1C) (Read, SPI Op-code 0xE4) Setting bits in the Interrupt Enable Register causes a hardware interrupt to be generated at the INT pin when the corresponding bits in the Interrupt Flag Register are set by HI-3110 as a result of the related events described below. Bit Name R/W ...
Page 26
... TXMTY is set and a message is loaded to the transmit FIFO, TXMTY will be automatically cleared by HI-3110). If individual bits in the Status Flag Enable Register STATFE are set, the STAT pin will pulse high when any of the enabled STATF bits are set. The value of individual bits in the STATF register may also be reflected on the GP1 and GP2 pins by setting the correct bit combinations in the General Purpose Pins Enable Register GPINE ...
Page 27
... SPI Po-code 0x1E) (Read, SPI Op-code 0xE6) Setting bits in the Status Flag Enable Register causes the STAT pin to go high when any of the corresponding bits in the Status Flag Register are set by HI-3110 as a result of the related events described below. Bit Name R/W ...
Page 28
... R/W Default Description 7-4 GPINE7:43:0 R/W 0000 Reflect status of interrupt flag bits in INTF or status flag bits in STATF on GP2 pin as follows: 3-0 GPINE3:0 R/W 0000 Reflect status of interrupt flag bits in INTF or status flag bits in STATF on GP1 pin as follow: HI-3110 GPINE7:4 GPINE3 MSB 0000: GP2 pin is asserted when F0MESS bit is set in register INTF. ...
Page 29
... SPI Op-code 0xFA) Bit Name R/W Default Description 7-0 T7:0 R/W 0x00 Free Running Timer Lower Byte, bits <7:0>. HI-3110 T15 LSB MSB The timer is clocked by the HI-3110 bit clock and continuously T7 LSB MSB HOLT INTEGRATED CIRCUITS 29 0 Note: A timer overrun is not 0 ...
Page 30
... CPHA (clock phase). The possible CPHA combinations define four possible "SPI Modes". Without describing details of the SPI modes, the HI-3110 operates in mode 0 where input data for each device (master and slave) is clocked on the rising edge of SCK, and output data for each device changes on the falling edge (CPHA = 0, CPOL = 0) ...
Page 31
... HOST SERIAL PERIPHERAL INTERFACE, cont. HI-3110 SPI COMMANDS For the HI-3110, each SPI read or write operation begins with an 8-bit command byte transferred from the host to the device after assertion Since HI-3110 command byte reception is half-duplex, the host discards the dummy byte it receives while serially transmitting the command byte ...
Page 32
... Read Bit Timing Register 1 Read Message Status Register Read Error Register Read Interrupt Flag Register Read Status Flag Register Read Interrupt Enable Register Read Status Flag Enable Register HOLT INTEGRATED CIRCUITS HI-3110 Command Data Field Hex 0x42 15 bytes 0x44 13 bytes 0x46 ...
Page 33
... TXEN & TX1M) Reset (Clear) Transmit FIFO (resets TXEN & TX1M, but completes current transmission) Master Reset Reset Time Tag Counter Reset Receive FIFO HOLT INTEGRATED CIRCUITS HI-3110 Command Data Field Hex 0xE8 1 byte (see GPINE Register Definition) 0xEA 1 byte ...
Page 34
... Write Mask 2 ID Write Mask 3 ID Write Mask 4 ID Write Mask 5 ID Write Mask 6 ID Write Mask 7 ID HOLT INTEGRATED CIRCUITS HI-3110 Command Data Field Hex 0x12 bytes) for Std frame bytes) for Ext frame (N = number of loaded messages ...
Page 35
... Table 2(a). For extended frames, the SPI data field has the format shown in Table 2(b). automatically interpret Standard or Extended frames by decoding the IDE bit. The HI-3110 also decodes the data length code (DLC) and ignores data bytes greater than the DLC value ( Note: assumed to be equal to 8) ...
Page 36
... HI-3110 Transmit Message Flow Diagram HI-3110 HOLT INTEGRATED CIRCUITS 36 ...
Page 37
... Note: The Message Tag is a host-assigned identifier that is stored along with a time tag in the Transmit History FIFO. It can be used by the host to log successfully transmitted messages at a later time. HI-3110 Table 2. SPI Transmit Data Format Bit Description (”x” = Don’t care) ...
Page 38
... Note: The Message Tag is a host-assigned identifier that is stored along with a time tag in the Transmit History FIFO. It can be used by the host to log successfully transmitted messages at a later time. HI-3110 Table 2. SPI Transmit Data Format Bit Description (”x” = Don’t care ...
Page 39
... FILHIT2:0 bits. As can be seen in Table 5, bits specific to extended frames will be read as zeros for standard frames. If the received data does not contain an 8 byte payload (8 data bytes), the HI-3110 will pad the remaining data bytes with zeros. The host should keep the SPI sequence. ...
Page 40
... Match ? No ID Acceptance Filter 1 ID Mask Filter 1 Yes Match ? No ID Acceptance Filter 7 ID Mask Filter 7 Yes Match ? No Message not stored Figure 13. Receive Buffer Structure HOLT INTEGRATED CIRCUITS HI-3110 MESSTAT Register FILHIT3:0 bits FILHIT3:0 = 1000 FILHIT3:0 = 1001 FILHIT3:0 = 1111 40 Load Receive FIFO ...
Page 41
... Standard ID) 3 ID14 to ID7 (Note: Written as zeros for Standard ID) 4 ID6 to ID0 (Note: Written as zeros for Standard ID) 5 Data Byte 1 6 Data Byte 2 HI-3110 Bit Description (”x” = Don’t care) Bit Description (”x” = Don’t care) HOLT INTEGRATED CIRCUITS ...
Page 42
... Data Byte 1 10 Data Byte 2 11 Data Byte 3 12 Data Byte 4 13 Data Byte 5 14 Data Byte 6 15 Data Byte 7 16 Data Byte 8 HI-3110 Bit Description (”x” = Don’t care) HOLT INTEGRATED CIRCUITS ...
Page 43
... TIMING DIAGRAMS CS t CHH SCK SCKH SCKL SCK SO Hi Impedance HI-3110 SERIAL INPUT TIMING DIAGRAM t CSS t t SCKR DH MSB SERIAL OUTPUT TIMING DIAGRAM t DV MSB HOLT INTEGRATED CIRCUITS 43 t CPH t t SCKF CSH LSB t CPH t CHZ LSB Hi Impedance ...
Page 44
... Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. These are stress ratings only. Functional operation of the device at these or any other conditions above those indicated in the operational sections of the specifications is not implied. Exposure to absolute maximum rating conditions for extended periods may affect device reliability. HI-3110 Operating Temperature Range: (Industrial).........................-40°C to +85°C -58V to +58V Maximum Junction Temperature +0 ...
Page 45
... Logic Outputs High-Level Output Voltage Low-Level Output Voltage Output sink current Output source current SO Output Leakage Oscillator Pins OSCIN Feedback Resistor OSCOUT Drive Current HI-3110 CONDITIONS SYMBOL V LOGIC V DD All inputs/outputs open except the oscillator configured for 24MHz and with 60 Ohm resistors at CANH and ...
Page 46
... Common mode input resistance Deviation between common mode input resistance Differential input resistance SPLIT pin output voltage 1 Common mode input capacitance (1Mbit/s data rate) 1 Differential input capacitance (1Mbit/s data rate) HI-3110 CONDITIONS SYMBOL VO(CANH) See Fig 14 VO(CANL) VOM See Fig. 14 ...
Page 47
... SCK falling edge CS inactive between SPI instructions SPI SI Data set-up time to SCK rising edge SPI SI Data hold time after SCK rising edge SO high-impedance after SCK falling edge CAN Bus Data Rate Time Out HI-3110 SYMBOL SCK clock frequency f SCK SCK clock period t CYC ...
Page 48
... HI-3110 Internal transceiver O(CANL) Dominant Recessive Figure 14. CAN Bus Driver Circuit Internal W 300 CANH transceiver DIFF(d)(o) L CANL W 300 Figure 15. CAN Bus Driver (Dominant) Test Circuit Internal CANH transceiver 0V CANL Figure 16. CAN Bus Driver Short-Circuit Test HOLT INTEGRATED CIRCUITS 48 V DIFF(d)(o) ...
Page 49
... Figure 17. Split-Termination Connection CANH V DIFF(d)( DIFF(d)(i) I(CANH) I(CANL) CANL V I(CANL) Figure 18. CAN Bus Receiver Common Mode Voltage Test OSCIN HI-3110 OSCOUT 1 10pF typ. Figure 19. Suggested Crystal Oscillator Circuit HOLT INTEGRATED CIRCUITS Internal Transceiver RXD C1 Crystal R Resonator ...
Page 50
... OSCI 3 GP1 3113PCx GP2 6 TXEN 7 CLKOUT Pin Plastic QFN, 7mm x 7mm HI-3110 18 INT VLOGIC OSCOUT OSCIN GP1 GP2 5 13 SCK TXEN 6 12 STAT CLKOUT 7 11 TXD GND CANL 9 18-Pin Plastic SOIC - WB Package ...
Page 51
... ORDERING INFORMATION HI - 311x PART NUMBER PART NUMBER PART NUMBER PART NUMBER HI-3110 LEAD FINISH Tin / Lead (Sn / Pb) Solder Blank 100% Matte Tin (Pb-free, RoHS compliant) F TEMPERATURE RANGE FLOW I -40°C TO +85°C T -55°C TO +125°C M -55°C TO +125°C ...
Page 52
... REVISION HISTORY P/N Rev Date Description of Change DS3110 New 09/7/10 Initial Release. A 09/27/11 Updated DC Electrical Characteristics Table. Added “M grade” part to ordering information. Added this revision history page. HI-3593 HOLT INTEGRATED CIRCUITS 52 ...
Page 53
... PLASTIC SMALL OUTLINE (SOIC (Wide Body) (11.531 ± .20) .4065 ± .0125 (10.325 ± .32) .050 BSC (1.27) BSC = “Basic Spacing between Centers” is theoretical true position dimension and has no tolerance. (JEDEC Standard 95) 44-PIN PLASTIC CHIP-SCALE PACKAGE .276 BSC (7.00) .276 Top View BSC (7.00) .039 max (1.00) BSC = “ ...