K4S560432A-TC/L1H SAMSUNG [Samsung semiconductor], K4S560432A-TC/L1H Datasheet - Page 6

• Manufacturer Part Number: K4S560432A-TC/L1H
• Description: 256Mbit SDRAM 16M x 4bit x 4 Banks Synchronous DRAM LVTTL
• Manufacturer: SAMSUNG [Samsung semiconductor]

AC OPERATING TEST CONDITIONS
Notes :
K4S560432A
OPERATING AC PARAMETER
(AC operating conditions unless otherwise noted)
AC input levels (Vih/Vil)
Input timing measurement reference level
Input rise and fall time
Output timing measurement reference level
Output load condition
Row active to row active delay
RAS to CAS delay
Row precharge time
Row active time
Row cycle time
Last data in to row precharge
Last data in to Active delay
Last data in to new col. address delay
Last data in to burst stop
Col. address to col. address delay
Number of valid output data
Output
1. The minimum number of clock cycles is determined by dividing the minimum time required with clock cycle time
2. Minimum delay is required to complete write.
3. All parts allow every cycle column address change.
4. In case of row precharge interrupt, auto precharge and read burst stop.
5. For -80/1H/1L, tRDL=1CLK and tDAL=1CLK+20ns is also supported .
(Fig. 1) DC output load circuit
and then rounding off to the next higher integer.
SAMSUNG recommends tRDL=2CLK and tDAL=2CLK + 20ns.
870
Parameter
Parameter
3.3V
1200
50pF
CAS latency=3
CAS latency=2
V
V
OH
OL
t
t
t
t
t
t
t
t
t
(DC) = 0.4V, I
RAS
(DC) = 2.4V, I
Symbol
RRD
RCD
t
RAS
t
CCD
(V
RDL
DAL
CDL
BDL
RP
RC
DD
(min)
(min)
(max)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
(min)
= 3.3V
OL
OH
0.3V, T
= 2mA
-75
= -2mA
15
20
20
45
65
A
= 0 to 70 C)
-
See Fig. 2
tr/tf = 1/1
2.4/0.4
Value
1.4
1.4
-80
16
20
20
48
68
2 CLK + 20 ns
Output
Version
100
2
1
1
1
2
-1H
(Fig. 2) AC output load circuit
20
20
20
50
70
1
Z0 = 50
Rev. 0.0 Sep. 1999
-1L
20
20
20
50
70
CMOS SDRAM
Unit
CLK
CLK
CLK
CLK
ns
ns
ns
ns
us
ns
ea
-
Vtt = 1.4V
Unit
50
ns
50pF
V
V
V
Note
2,5
1
1
1
1
1
5
2
2
3
4