RHF1201_11 STMICROELECTRONICS [STMicroelectronics], RHF1201_11 Datasheet - Page 26

• Manufacturer Part Number: RHF1201_11
• Description: Rad-hard 12-bit 50 Msps A/D converter
• Manufacturer: STMICROELECTRONICS [STMicroelectronics]

Electrical characteristics (unchanged after 300 kRad)
7.4
26/34
Clock input
The quality of the converter very much depends on the accuracy of the clock input in terms
of jitter. The use of a low jitter, crystal-controlled oscillator is recommended.
The following points should also be considered.
●
●
●
●
Figure 57. Clock input schematic
The signal applied to the CLK pin is critical to obtain full performance from the RHF1201.
We recommend using a 0 to 2.5 V square signal with fast transition times, and to place
proper termination resistors as close as possible to the device.
The sampling instant is determined by the rising edge of the clock signal. The jitter
associated with this instant must be as low as possible to avoid SNR degradation on
fast-moving input signals. To ensure that LSB errors stay below 0.5, the total jitter T
satisfy the following condition for a full-scale input signal.
n being the number of bits.
In most cases, the clock signal jitter is the major contributor of total noise. Therefore,
particular attention should be given to the clock signal when acquiring fast signals with a
low-frequency clock.
Square clock
DVcc/2
DVcc/2
At 45 Msps, the duty cycle must be between 45% and 65%.
The clock power supplies must be independent of the ADC output supplies to avoid
digital noise modulation on the output.
When powered-on, the circuit needs several clock periods to reach its normal operating
conditions.
The clock input is a MOS input. To bias this input stage properly, a bias current of 10 nA
is sufficient.
Sine clock
Short track
Doc ID 12585 Rev 5
CLK
T
j
<
---------------------------------
π F
⋅
in
1
⋅
2
n
+
50 Ω clock generator
1
50 Ω
50 Ω
Short track
CLK
RHF1201
AM04551
j
must