HX640 LATTICE [Lattice Semiconductor], HX640 Datasheet - Page 9

• Manufacturer Part Number: HX640
• Manufacturer: LATTICE [Lattice Semiconductor]

iCE40 HX-Series Ultra-Low Power mobileFPGA
Lattice Semiconductor Corporation
www.latticesemi.com/
Frequency Range
F
F
Duty Cycle
PLL
Tw
Tw
PLL
Fine Delay
t
PLL
PLL
Jitter
PLL
PLL
Lock/Reset Time
t
tw
Symbol
FDTAP
LOCK
Phase-Locked Loop (PLL) Block
REF
OUT
1.
2. The output jitter specification refers to the intrinsic jitter of the PLL.
RST
HI
LOW
Table 11
Notes:
IJ
OJ
TAPS
FDAM
IPJ
OPJ
Output jitter performance is affected by input jitter. A clean reference clock < 100ps jitter must be used to ensure
best jitter performance.
From
provides timing information for the Phase-Locked Loop (PLL) block shown in
To
Input clock frequency range
Output clock frequency range (cannot exceed
maximum frequency supported by global
buffers)
Input duty cycle
Input clock high time
Input clock low time
Output duty cycle
Fine delay adjustment, per tap
Fine delay adjustment settings
Maximum delay adjustment
Input clock period jitter
PLLOUT output period jitter
PLL lock time after receive stable, monotonic
REFERENCECLK input
Minimum reset pulse width
Table 11:
Figure 10:
Description
Phase-Locked Loop (PLL) Block Timing
LATCHINPUTVALUE
DYNAMICDELAY[3:0]
EXTFEEDBACK
BYPASS
RESET
REFERENCECLK
Phase-Locked Loop (PLL)
Nominal VCC
PLL
PLLOUT
LOCK
™
Family
Min.
2.5
2.5
10
16
35
45
20
—
—
—
0
Typical
1% or
≤ 100
1.2 V
165
2.5
—
—
—
—
—
—
—
—
—
—
Figure
(1.31, 30-MAR-2012)
10.
+/- 1.1%
period or
+/- 300
output
≥ 110
Max.
133
533
65
55
15
50
—
—
—
Units
MHz
MHz
taps
μs
%
ns
ns
%
ps
ns
ps
ps
ns
9