EDD5108ADTA-7A ELPIDA [Elpida Memory], EDD5108ADTA-7A Datasheet - Page 14

• Manufacturer Part Number: EDD5108ADTA-7A
• Description: 512M bits DDR SDRAM
• Manufacturer: ELPIDA [Elpida Memory]

Row address strobe and bank activate [ACT]
This command activates the bank that is selected by BA0, BA1 and determines the row address (AX0 to AX12).
(See Bank Select Signal Table)
Precharge selected bank [PRE]
This command starts precharge operation for the bank selected by BA0, BA1. (See Bank Select Signal Table)
[Bank Select Signal Table]
Bank 0
Bank 1
Bank 2
Bank 3
Remark: H: VIH. L: VIL
Precharge all banks [PALL]
This command starts a precharge operation for all banks.
Refresh [REF/SELF]
This command starts a refresh operation. There are two types of refresh operation, one is auto-refresh, and another
is self-refresh. For details, refer to the CKE truth table section.
Mode register set/Extended mode register set [MRS/EMRS]
The DDR SDRAM has the two mode registers, the mode register and the extended mode register, to defines how it
works. The both mode registers are set through the address pins (the A0 to the A12, BA0 to BA1) in the mode
register set cycle. For details, refer to "Mode register and extended mode register set".
CKE Truth Table
Current state
Idle
Idle
Idle
Self refresh
Power down
Remark:
Notes: 1. All the banks must be in IDLE before executing this command.
Data Sheet E0384E30 (Ver. 3.0)
2. The CKE level must be kept for 1 CK cycle at least.
H: VIH. L: VIL.
Command
Auto-refresh command (REF)
Self-refresh entry (SELF)
Power down entry (PDEN)
Self refresh exit (SELFX)
Power down exit (PDEX)
: VIH or VIL.
EDD5104ADTA, EDD5108ADTA, EDD5116ADTA
BA0
L
H
L
H
CKE
n – 1
H
H
H
H
L
L
L
L
14
n
H
L
L
L
H
H
H
H
/CS
L
L
L
H
L
H
L
H
/RAS
L
L
H
H
H
BA1
L
L
H
H
/CAS
L
L
H
H
H
/WE
H
H
H
H
H
Address
Notes
2
1, 2