SI8440 SILABS [Silicon Laboratories], SI8440 Datasheet - Page 16

• Manufacturer Part Number: SI8440
• Description: QUAD-CHANNEL DIGITAL ISOLATOR
• Manufacturer: SILABS [Silicon Laboratories]

Si8440/1/2
4. Layout Recommendations
Dielectric isolation is a set of specifications produced by
the safety regulatory agencies from around the world
that describes the physical construction of electrical
equipment that derives power from a high-voltage
power system such as 100–240 V
industrial power systems. The dielectric test (or HIPOT
test) given in the safety specifications places a very high
voltage between the input power pins of a product and
the user circuits and the user touchable surfaces of the
product. For the IEC relating to products deriving their
power from the 220–240 V power grids, the test voltage
is 2500 V
voltage).
There
specifications:
Figure 14 illustrates the accepted method of providing
the proper creepage distance along the surface. For a
220–240 V application, this distance is 8 mm and the
wide body SOIC package must be used. There must be
no copper traces within this 8 mm exclusion area, and
the surface should have a conformal coating such as
solder resist. The digital isolator chip must straddle this
exclusion area.
16
Creepage—the distance along the insulating surface
an arc may travel.
Clearance—the distance through the shortest path
through air that an arc may travel.
are
Figure 14. Creepage Distance
AC
two
(or 3750 V
terms
described
DC
—the peak equivalent
AC
in
systems or
the
safety
Rev. 0.3
4.1. Supply Bypass
The Si8440 requires a 0.1 µF bypass capacitor between
V
should be placed as close as possible to the package.
4.2. Input and Output Characteristics
The Si8440 inputs and outputs are standard CMOS
drivers/receivers.
4.3. Enable Inputs
The receiver output drivers are enabled when the
Enable input is high and the drivers remain in a high-
impedance state when Enable is low. The Enable input
can be used for multiplexing or as a clock sync input.
Supply currents remain at their nominal values when
Enable is low. The Enable inputs must be tied to a logic
level.
DD1
and GND1 and V
DD2
and GND2. The capacitor