85108AGILFT IDT, 85108AGILFT Datasheet

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85108AGILFT

Manufacturer Part Number
85108AGILFT
Description
Clock Drivers & Distribution DIFFERENTIAL CLOCK
Manufacturer
IDT
Datasheet

Specifications of 85108AGILFT

Rohs
yes
Part # Aliases
ICS85108AGILFT
General Description
levels and translates them to 3.3V HCSL output levels. The
ICS85108I provides a low power, low noise, low skew, point-to-point
solution for distributing HCSL clock signals.
Guaranteed output and part-to-part skew specifications make the
ICS85108I ideal for those applications demanding well defined
performance and repeatability.
Block Diagram
ICS85108AGI REVISION A OCTOBER 23, 2009
IREF
CLK
HiPerClockS™
ICS
Pulldown
Pullup/Pulldown
The ICS85108I is a low skew, high performance 1-to-8
Differential-to-0.7V HCSL Clock Distribution Chip and
a member of the HiPerClockS™ family of High
Performance Clock Solutions from IDT. The ICS85108I
CLK, nCLK pair can accept most differential input
Low Skew, 1-to-8, Differential-to-0.7V HCSL
Clock Distribution Chip
Q0
Q1
Q2
Q3
Q4
Q5
Q6
Q7
nQ0
nQ1
nQ2
nQ3
nQ4
nQ5
nQ6
nQ7
1
Features
Eight 0.7V differential HCSL clock output pairs
CLK/nCLK input pair can accept the following differential input
levels: LVPECL, LVDS, LVHSTL, SSTL, HCSL
Maximum output frequency: 500MHz
Additive phase jitter, RMS: 0.09ps (typical)
Output skew: 80ps (maximum)
Part-to-part skew: 400ps (maximum)
Propagation delay: 3ns (maximum)
Full 3.3V operating supply
-40°C to 85°C ambient operating temperature
Available in both standard (RoHS 5) and lead-free (RoHS 6)
packages
4.4mm x 7.8mm x 0.925mm package body
Pin Assignment
24-Lead TSSOP, 173-MIL
IREF
CLK
nQ0
nQ1
nQ2
nQ3
V
Q0
Q1
Q2
Q3
DD
ICS85108I
G Package
Top View
1
2
3
4
5
6
7
8
9
10
11
12
©2009 Integrated Device Technology, Inc.
24
23
22
21
20
19
18
17
16
15
14
13
Q7
GND
V
Q5
V
Q4
nQ7
Q6
nQ6
GND
DD
DD
ICS85108I
DATA SHEET

Related parts for 85108AGILFT

85108AGILFT Summary of contents

Page 1

... Differential-to-0.7V HCSL Clock Distribution Chip and a member of the HiPerClockS™ family of High HiPerClockS™ Performance Clock Solutions from IDT. The ICS85108I CLK, nCLK pair can accept most differential input levels and translates them to 3.3V HCSL output levels. The ICS85108I provides a low power, low noise, low skew, point-to-point solution for distributing HCSL clock signals ...

Page 2

ICS85108I Data Sheet Table 1. Pin Descriptions Number Name 1, 2 Q0, nQ0 Output 3, 16 Power DD 4 CLK Input 5 nCLK Input 6, 7 Q1, nQ1 Output 8, 9 Q2, nQ2 Output 10 IREF 11, 12 ...

Page 3

ICS85108I Data Sheet Absolute Maximum Ratings NOTE: Stresses beyond those listed under Absolute Maximum Ratings may cause permanent damage to the device. These ratings are stress specifications only. Functional operation of product at these conditions or any conditions beyond those ...

Page 4

ICS85108I Data Sheet AC Electrical Characteristics Table 5. HCSL AC Characteristics, V Symbol Parameter f Output Frequency MAX t Propagation Delay; NOTE 1 PD tsk(o) Output Skew; NOTE 2, 3 tsk(pp) Part-to-Part Skew; NOTE 3, 4 Buffer Additive Phase Jitter, ...

Page 5

ICS85108I Data Sheet Additive Phase Jitter The spectral purity in a band at a specific offset from the fundamental compared to the power of the fundamental is called the dBc Phase Noise. This value is normally expressed using a Phase ...

Page 6

ICS85108I Data Sheet Parameter Measurement Information 3.3V±10% 50Ω 33Ω 49.9Ω HCSL 50Ω 33Ω IREF GND 49.9Ω 475Ω 0V Output Load AC Test Circuit V DD nCLK V Cross Points PP CLK GND Differential Input Level Par t 1 ...

Page 7

ICS85108I Data Sheet Parameter Measurement Information, continued Clock Period (Differential) Positive Duty Cycle (Differential) 0.0V Q/nQ Differential Measurement Points for Duty Cycle/Period Rise Edge Rate +150mV 0.0V -150mV Differential Measurement Points for Rise/Fall Edge Rate T STABLE ...

Page 8

ICS85108I Data Sheet Application Information Wiring the Differential Input to Accept Single Ended Levels Figure 1 shows how the differential input can be wired to accept single ended levels. The reference voltage V_REF = V generated by the bias resistors ...

Page 9

... ICS85108AGI REVISION A OCTOBER 23, 2009 LOW SKEW, 1-TO-8, DIFFERENTIAL-TO-0.7V HCSL CLOCK DISTRIBUTION CHIP component to confirm the driver termination requirements. For example, in Figure 2A, the input termination applies for IDT PP HiPerClockS open emitter LVHSTL drivers. If you are using an LVHSTL driver from another vendor, use their termination recommendation ...

Page 10

ICS85108I Data Sheet Recommended Termination Figure 3A is the recommended termination for applications which require the receiver and driver separate PCB. All traces should be 50Ω impedance. Figure 3A. Recommended Termination Figure 3B is the recommended ...

Page 11

ICS85108I Data Sheet Power Considerations This section provides information on power dissipation and junction temperature for the ICS85108I. Equations and example calculations are also provided. 1. Power Dissipation. The total power dissipation for the ICS85108I is the sum of the ...

Page 12

ICS85108I Data Sheet 3. Calculations and Equations. The purpose of this section is to calculate power dissipation on the IC per HCSL output pair. HCSL output driver circuit and termination are shown in Figure OUT = ...

Page 13

ICS85108I Data Sheet Reliability Information θ Table 7. vs. Air Flow Table for a 24 Lead TSSOP JA Meters per Second Multi-Layer PCB, JEDEC Standard Test Boards Transistor Count The transistor count for ICS85108I is: 583 Package Outline and Package ...

Page 14

... ICS85108AGI 85108AGILF ICS85108AGILF 85108AGILFT ICS85108AGILF NOTE: Parts that are ordered with an "LF" suffix to the part number are the Pb-Free configuration and are RoHS compliant. While the information presented herein has been checked for both accuracy and reliability, Integrated Device Technology (IDT) assumes no responsibility for either its use or for the infringement of any patents or other rights of third parties, which would result from its use ...

Page 15

ICS85108I Data Sheet Revision History Sheet Rev Table Page Description of Change T1 2 Pin Description Table - corrected sequence of pin names to correspond to Pin A Assignment. Pin 13 should be nQ4 and pin 14 should be Q4. ...

Page 16

... IDT or any third parties. IDT’s products are not intended for use in life support systems or similar devices where the failure or malfunction of an IDT product can be reasonably expected to significantly affect the health or safety of users. Anyone using an IDT product in such a manner does so at their own risk, absent an express, written agreement by IDT ...

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