MAX11138ATI+ Maxim Integrated, MAX11138ATI+ Datasheet - Page 18

• Manufacturer Part Number: MAX11138ATI+
• Description: Analog to Digital Converters - ADC 500ksps, Low-Power, Serial 12-/10-/8-Bit
• Manufacturer: Maxim Integrated

Specifications of MAX11138ATI+

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 500 kSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 61.7 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-28
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

The ADC’s input-tracking circuitry features a 1.5MHz,
small-signal, full-linear bandwidth to digitize high-speed
transient events and measure periodic signals with
bandwidths exceeding the ADC’s sampling rate by using
undersampling techniques. Anti-alias filtering of the input
signals is necessary to avoid high-frequency signals
aliasing into the frequency band of interest.
The MAX11135–MAX11143 feature a serial interface
compatible with SPI/QSPI and MICROWIRE devices. For
SPI/QSPI, ensure the CPU serial interface runs in master
mode to generate the serial clock signal. Select the SCLK
frequency of 8MHz or less, and set clock polarity (CPOL)
and phase (CPHA) in the FP control registers to the same
value. The MAX11135–MAX11143 operate with SCLK
idling high, and thus operate with CPOL = CPHA = 1.
Set CS low to latch input data at DIN on the rising edge
of SCLK. Output data at DOUT is updated on the falling
Figure 2a. External Clock Mode Timing Diagram with CHAN_ID=1
Figure 2b. External Clock Mode Timing Diagram with CHAN_ID=1 for Best Performance
DOUT
SCLK
DOUT
SCLK
DIN
DIN
CS
CS
1
1
Ch[3]
Ch[3]
DI[15]
DI[15]
2
2
Ch[2]
Ch[2]
DI[14]
500ksps, Low-Power, Serial 12-/10-/8-Bit,
3
3
Ch[1] Ch[0]
Ch[1] Ch[0]
3-Wire Serial Interface
4
4
Input Bandwidth
5
5
MSB MSB-1
MSB MSB-1
6
6
7
7
8
8
9
9
10
10
edge of SCLK. A high-to-low transition on CS samples
the analog inputs and initiates a new frame. A frame is
defined as the time between two falling edges of CS.
There is a minimum of 16 bits per frame. The serial data
input, DIN, carries data into the control registers clocked
in by the rising edge of SCLK. The serial data output,
DOUT, delivers the conversion results and is clocked out
by the falling edge of SCLK. DOUT is a 16-bit data word
containing a 4-bit channel address, followed by a 12-bit
conversion result led by the MSB when CHAN_ID is set
to 1 in the ADC Mode Control register
this mode, keep the clock high for at least one full SCLK
period before the CS falling edge to ensure best perfor-
mance
clock mode only), the 16-bit data word includes a leading
zero and the 12-bit conversion result is followed by 3 trail-
ing zeros
are set to 0. In the 8-bit ADC, the last 4 LSBs are set to 0.
11
11
MAX11135–MAX11143
4-/8-/16-Channel ADCs
(Figure
12
12
(Figure
13
13
2b). When CHAN_ID is set to 0 (external
2c). In the 10-bit ADC, the last 2 LSBs
14
14
15
15
LSB+1
LSB+1
DI[1]
DI[1]
16
16
LSB
DI[0]
LSB
DI[0]
t
QUIET
> t
SCLK
(Figure
2a). In
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