MAX11138ATI+ Maxim Integrated, MAX11138ATI+ Datasheet - Page 34

• Manufacturer Part Number: MAX11138ATI+
• Description: Analog to Digital Converters - ADC 500ksps, Low-Power, Serial 12-/10-/8-Bit
• Manufacturer: Maxim Integrated

Specifications of MAX11138ATI+

• Rohs: yes
• Number Of Channels: 4/2
• Architecture: SAR
• Conversion Rate: 500 kSPs
• Resolution: 10 bit
• Input Type: Single-Ended/Differential
• Snr: 61.7 dB
• Interface Type: 3-Wire, QSPI, SPI
• Operating Supply Voltage: 2.35 V to 3.6 V
• Maximum Operating Temperature: + 125 C
• Mounting Style: SMD/SMT
• Package / Case: TQFN-28
• Maximum Power Dissipation: 2758 mW
• Minimum Operating Temperature: - 40 C
• Number Of Converters: 1
• Voltage Reference: 1 V

Figure 10. SampleSet Timing Diagram
Upon receiving the SampleSet pattern, the user can
set the ADC Mode Control register to begin the conver-
sion process where data readout begins with the first
SampleSet entry. While the last conversion result is read,
the ADC can be instructed to enter AutoShutdown, if
desired. If the user wishes to change the SampleSet
length, a new pattern must be loaded into the ADC as
described in
1) Configure the ADC (set the MSB on DIN to 1).
2) Program ADC mode control (set the MSB on DIN to 0)
See
to begin the conversion process or to control power
management features.
• If ADC mode control is written during a conversion
• If configuration data (MSB on DIN is a 1) is written
DOUT
SCLK
Figure 11
DIN
CS
sequence, the ADC finishes the present conver-
sion and at the next falling edge of CS initiates its
new instruction.
during a conversion sequence, the ADC finishes
the present conversion in the existing scan mode.
However, data on DOUT is not valid in following
frames until a new ADC mode control instruction
is coded.
Programming Sequence Flow Chart
1
Figure
for programming sequence.
Applications Information
10.
WRITE SampleSet REGISTER
500ksps, Low-Power, Serial 12-/10-/8-Bit,
DEFINE SEQ_LENGTH
How to Program Modes
16
1
ENTRY 1
RISING EDGE DEPENDS ON SEQ_LENGTH
For best performance, use PCBs with a solid ground
plane. Ensure that digital and analog signal lines are
separated from each other. Do not run analog and digital
(especially clock) lines parallel to one another or digital
lines underneath the ADC package. Noise in the V
OVDD, and REF affects the ADC’s perfor mance. Bypass
the V
bypass capacitors. Minimize capacitor lead and trace
lengths for best supply-noise rejection.
It is important to match the settling time of the input
amplifier to the acquisition time of the ADC. The conver-
sion results are accurate when the ADC samples the
input signal for an interval longer than the input signal’s
worst-case settling time. By definition, settling time is
the interval between the application of an input voltage
step and the point at which the output signal reaches
and stays within a given error band centered on the
resulting steady-state amplifier output level. The ADC
input sampling capacitor charges during the sampling
cycle, referred to as the acquisition period. During this
acquisition period, the settling time is affected by the
input resistance and the input sampling capacitance.
This error can be estimated by looking at the settling
of an RC time constant using the input capacitance
and the source impedance over the acquisition time
period.
MAX4430, offering a settling time of 37ns at 16-bit reso-
lution, is an excellent choice for this application. See the
THD vs. Input Resistance graph in the
Characteristics.
TIME BETWEEN CS FALLING AND
ENTRY 2
LOAD SampleSet PATTERN
MAX11135–MAX11143
DD
4-/8-/16-Channel ADCs
Figure 13
, OVDD, and REF to ground with 0.1FF and 10FF
Layout, Grounding, and Bypassing
ENTRY N = (SEQ_LENGTH)
shows a typical application circuit. The
Choosing an Input Amplifier
OR CONTINUE WITH ADDITIONAL
WRITE ADC MODE CONTROL
CONFIGURATION SETTINGS
1
Typical Operating
DD
34
,