SSTU32865ET/G,518 NXP Semiconductors, SSTU32865ET/G,518 Datasheet - Page 7

IC REG BUFFER 28BIT 160-TFBGA

SSTU32865ET/G,518

Manufacturer Part Number
SSTU32865ET/G,518
Description
IC REG BUFFER 28BIT 160-TFBGA
Manufacturer
NXP Semiconductors
Datasheet

Specifications of SSTU32865ET/G,518

Logic Type
1:2 Registered Buffer with Parity
Package / Case
160-TFBGA
Supply Voltage
1.7 V ~ 1.9 V
Number Of Bits
28
Operating Temperature
0°C ~ 70°C
Mounting Type
Surface Mount
Logic Family
SSTU
Number Of Circuits
1
Maximum Clock Frequency
450 MHz
Propagation Delay Time
1.8 ns
High Level Output Current
- 8 mA
Low Level Output Current
8 mA
Supply Voltage (max)
1.9 V
Maximum Operating Temperature
+ 70 C
Minimum Operating Temperature
0 C
Mounting Style
SMD/SMT
Supply Voltage (min)
1.7 V
Function
Registered Buffer
Lead Free Status / RoHS Status
Lead free / RoHS Compliant
Lead Free Status / RoHS Status
Lead free / RoHS Compliant, Lead free / RoHS Compliant
Other names
935275433518
SSTU32865ET/G-T
SSTU32865ET/G-T

Available stocks

Company
Part Number
Manufacturer
Quantity
Price
Part Number:
SSTU32865ET/G,518
Manufacturer:
NXP Semiconductors
Quantity:
10 000
Philips Semiconductors
Table 2:
9397 750 13799
Product data sheet
Symbol
Clock inputs
CK, CK
Miscellaneous inputs
m.c.l.
m.c.h.
RESET
VREF
VDDL
VDDR
GND
n.c.
Pin description
Pin
J1, K1
U3, V2, V3
U5, V5
L1
A1, V1
D4, E4, E6, F4, G4, H4, K4,
K5, N4, N5, P5, P6, R5, R6
E7, F8, F9, G8, G9, J8, J9,
L8, L9, N8, N9, P7, P8
D5, D8, D9, E5, E8, E9, F5,
G5, H5, H8, H9, J4, J5, K8,
K9, L4, L5, M4, M5, M8, M9,
P4, P9, R4, R7, R8, R9
A2, A4, A5, B3, B4, B5, D6,
D7, V4
…continued
Rev. 02 — 28 September 2004
Type
SSTL_18
1.8 V
LVCMOS
0.9 V
nominal
Description
Differential master clock input pair to the register. The
register operation is triggered by a rising edge on the
positive clock input (CK).
Must be connected to a logic LOW
Must be connected to a logic HIGH.
Asynchronous reset input. When LOW, it causes a reset
of the internal latches, thereby forcing the outputs LOW.
RESET also resets the PTYERR signal.
Input reference voltage for the SSTL_18 inputs. Two pins
(internally tied together) are used for increased reliability.
power supply voltage
power supply voltage
ground
ball present but not connected to die
1.8 V DDR registered buffer with parity
© Koninklijke Philips Electronics N.V. 2004. All rights reserved.
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