IDT74SSTUBF32866BBFG8 IDT, Integrated Device Technology Inc, IDT74SSTUBF32866BBFG8 Datasheet - Page 12

• Manufacturer Part Number: IDT74SSTUBF32866BBFG8
• Description: IC BUFFER 25BIT CONF DDR2 96BGA
• Manufacturer: IDT, Integrated Device Technology Inc

Specifications of IDT74SSTUBF32866BBFG8

• Logic Type: 1:1, 1:2 Configurable Registered Buffer
• Supply Voltage: 1.7 V ~ 1.9 V
• Number Of Bits: 25, 14
• Operating Temperature: 0°C ~ 70°C
• Mounting Type: Surface Mount
• Package / Case: 96-BGA
• Logic Family: SSTU
• Logical Function: Registered Buffer
• Number Of Elements: 1
• Number Of Inputs: 25
• Number Of Outputs: 25
• High Level Output Current: -8mA
• Low Level Output Current: 8mA
• Propagation Delay Time: 3ns
• Operating Supply Voltage (typ): 1.8V
• Operating Supply Voltage (max): 1.9V
• Operating Supply Voltage (min): 1.7V
• Clock-edge Trigger Type: Posit/Negat-Edge
• Polarity: Non-Inverting
• Technology: CMOS
• Frequency (max): 410(Min)MHz
• Mounting: Surface Mount
• Pin Count: 96
• Operating Temp Range: 0C to 70C
• Operating Temperature Classification: Commercial
• Lead Free Status / RoHS Status: Lead free / RoHS Compliant
• Other names: 74SSTUBF32866BBFG8

25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
IDT74SSTUBF32866B
25-BIT CONFIGURABLE REGISTERED BUFFER FOR DDR2
Terminal Functions
Terminal Name
CSR, DCS
Q1 - Q25
D1 - D25
PAR_IN
RESET
C0, C1
DODT
DCKE
QODT
QCKE
QERR
GND
V
QCS
PPO
CLK
CLK
V
Z
Z
REF
OH
DD
OL
Open Drain Output
Characteristics
Differential Input
Differential Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
SSTL_18 Input
LVCMOS Input
LVCMOS Input
Ground Input
1.8V nominal
0.9V nominal
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
1.8V CMOS
Electrical
Input
Input
Ground
Power Supply Voltage
Input Reference Clock
Reserved for future use
Reserved for future use
Positive Master Clock Input
Negative Master Clock Input
Configuration Control Inputs
Asynchronous Reset Input. Resets registers and disables V
data and clock differential-input receivers.
Chip Select Inputs. Disables outputs D1 - D24 output switching
when both inputs are HIGH.
Data Input. Clocked in on the crossing of the rising edge of CLK
and the falling edge of CLK.
The outputs of this register bit will not be suspended by the DCS
and CSR controls
The outputs of this register bit will not be suspended by the DCS
and CSR controls
Data Outputs that are suspended by the DCS and CSR controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Data Output that will not be suspended by the DCS and CSR
controls
Partial Parity Output. Indicates off parity of D1 - D25
Parity Input arrives one cycle after corresponding data input
Output Error bit, generated one cycle after the corresponding data
output
12
Description
COMMERCIAL TEMPERATURE GRADE
IDT74SSTUBF32866B
REF
7067/13